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Conferences in DBLP

2007 (conf/arc/2007)

  1. Frank Bouwens, Mladen Berekovic, Andreas Kanstein, Georgi Gaydadjiev
    Architectural Exploration of the ADRES Coarse-Grained Reconfigurable Array. [Citation Graph (0, 0)][DBLP]
    ARC, 2007, pp:1-13 [Conf]
  2. Mazen A. R. Saghir, Rawan Naous
    A Configurable Multi-ported Register File Architecture for Soft Processor Cores. [Citation Graph (0, 0)][DBLP]
    ARC, 2007, pp:14-25 [Conf]
  3. Kehuai Wu, Andreas Kanstein, Jan Madsen, Mladen Berekovic
    MT-ADRES: Multithreading on Coarse-Grained Reconfigurable Architecture. [Citation Graph (0, 0)][DBLP]
    ARC, 2007, pp:26-38 [Conf]
  4. Je-Hoon Lee, Seung-Sook Lee, Kyoung-Rok Cho
    Asynchronous ARM Processor Employing an Adaptive Pipeline Architecture. [Citation Graph (0, 0)][DBLP]
    ARC, 2007, pp:39-48 [Conf]
  5. Jae Young Hur, Stephan Wong, Stamatis Vassiliadis
    Partially Reconfigurable Point-to-Point Interconnects in Virtex-II Pro FPGAs. [Citation Graph (0, 0)][DBLP]
    ARC, 2007, pp:49-60 [Conf]
  6. Jae Young Hur, Todor Stefanov, Stephan Wong, Stamatis Vassiliadis
    Systematic Customization of On-Chip Crossbar Interconnects. [Citation Graph (0, 0)][DBLP]
    ARC, 2007, pp:61-72 [Conf]
  7. Saar Drimer
    Authentication of FPGA Bitstreams: Why and How. [Citation Graph (0, 0)][DBLP]
    ARC, 2007, pp:73-84 [Conf]
  8. Jae-Jin Lee, Dong-Guk Hwang, Gi-Yong Song
    Design of a Reversible PLD Architecture. [Citation Graph (0, 0)][DBLP]
    ARC, 2007, pp:85-90 [Conf]
  9. Kostas Siozios, Stelios Mamagkakis, Dimitrios Soudris, Antonios Thanailakis
    Designing Heterogeneous FPGAs with Multiple SBs. [Citation Graph (0, 0)][DBLP]
    ARC, 2007, pp:91-96 [Conf]
  10. Joonseok Park, Pedro C. Diniz
    Partial Data Reuse for Windowing Computations: Performance Modeling for FPGA Implementations. [Citation Graph (0, 0)][DBLP]
    ARC, 2007, pp:97-109 [Conf]
  11. Yazhuo Dong, Yong Dou, Jie Zhou
    Optimized Generation of Memory Structure in Compiling Window Operations onto Reconfigurable Hardware. [Citation Graph (0, 0)][DBLP]
    ARC, 2007, pp:110-121 [Conf]
  12. Rainer Scholz
    Adapting and Automating XILINX's Partial Reconfiguration Flow for Multiple Module Implementations. [Citation Graph (0, 0)][DBLP]
    ARC, 2007, pp:122-129 [Conf]
  13. Carlo Galuzzi, Koen Bertels, Stamatis Vassiliadis
    A Linear Complexity Algorithm for the Automatic Generation of Convex Multiple Input Multiple Output Instructions. [Citation Graph (0, 0)][DBLP]
    ARC, 2007, pp:130-141 [Conf]
  14. Kazunori Matsuyama, Motoki Amagasaki, Hideaki Nakayama, Ryoichi Yamaguchi, Masahiro Iida, Toshinori Sueyoshi
    Evaluating Variable-Grain Logic Cells Using Heterogeneous Technology Mapping. [Citation Graph (0, 0)][DBLP]
    ARC, 2007, pp:142-154 [Conf]
  15. Yong Dou, Jinhui Xu, Guiming Wu
    The Implementation of a Coarse-Grained Reconfigurable Architecture with Loop Self-pipelining. [Citation Graph (0, 0)][DBLP]
    ARC, 2007, pp:155-166 [Conf]
  16. Cesar Torres-Huitzil, Bernard Girau, Adrien Gauffriau
    Hardware/Software Codesign for Embedded Implementation of Neural Networks. [Citation Graph (0, 0)][DBLP]
    ARC, 2007, pp:167-178 [Conf]
  17. João Bispo, Ioannis Sourdis, João M. P. Cardoso, Stamatis Vassiliadis
    Synthesis of Regular Expressions Targeting FPGAs: Current Status and Open Issues. [Citation Graph (0, 0)][DBLP]
    ARC, 2007, pp:179-190 [Conf]
  18. Nicolas Hervé, Daniel Menard, Olivier Sentieys
    About the Importance of Operation Grouping Procedures for Multiple Word-Length Architecture Optimizations. [Citation Graph (0, 0)][DBLP]
    ARC, 2007, pp:191-200 [Conf]
  19. Ruzica Jevtic, Carlos Carreras, Gabriel Caffarena
    Switching Activity Models for Power Estimation in FPGA Multipliers. [Citation Graph (0, 0)][DBLP]
    ARC, 2007, pp:201-213 [Conf]
  20. Jean-Luc Beuchat, Takanori Miyoshi, Yoshihito Oyama, Eiji Okamoto
    Multiplication over Fpm on FPGA: A Survey. [Citation Graph (0, 0)][DBLP]
    ARC, 2007, pp:214-225 [Conf]
  21. Francisco Rodríguez-Henríquez, Guillermo Morales-Luna, Nazar A. Saqib, Nareli Cruz Cortés
    A Parallel Version of the Itoh-Tsujii Multiplicative Inversion Algorithm. [Citation Graph (0, 0)][DBLP]
    ARC, 2007, pp:226-237 [Conf]
  22. Edgar Ferrer, Dorothy Bollman, Oscar Moreno
    A Fast Finite Field Multiplier. [Citation Graph (0, 0)][DBLP]
    ARC, 2007, pp:238-246 [Conf]
  23. Rayan Chikhi, Steven Derrien, Auguste Noumsi, Patrice Quinton
    Combining Flash Memory and FPGAs to Efficiently Implement a Massively Parallel Algorithm for Content-Based Image Retrieval. [Citation Graph (0, 0)][DBLP]
    ARC, 2007, pp:247-258 [Conf]
  24. Javier Díaz, Eduardo Ros, Sonia Mota, Richard Carrillo
    Image Processing Architecture for Local Features Computation. [Citation Graph (0, 0)][DBLP]
    ARC, 2007, pp:259-270 [Conf]
  25. Günter Knittel
    A Compact Shader for FPGA-Based Volume Rendering Accelerators. [Citation Graph (0, 0)][DBLP]
    ARC, 2007, pp:271-282 [Conf]
  26. Yong-min Lee, Chang-Seok Choi, Seung-Gon Hwang, Hyun Dong Kim, Chul Hong Min, Jae-Hyun Park, Hanho Lee, Tae-Seon Kim, Chong Ho Lee
    Ubiquitous Evolvable Hardware System for Heart Disease Diagnosis Applications. [Citation Graph (0, 0)][DBLP]
    ARC, 2007, pp:283-292 [Conf]
  27. Xiaodong Yang, Shengmei Mou, Yong Dou
    FPGA-Accelerated Molecular Dynamics Simulations: An Overview. [Citation Graph (0, 0)][DBLP]
    ARC, 2007, pp:293-301 [Conf]
  28. David B. Thomas, Wayne Luk, Michael Stumpf
    Reconfigurable Hardware Acceleration of Canonical Graph Labelling. [Citation Graph (0, 0)][DBLP]
    ARC, 2007, pp:302-313 [Conf]
  29. Nilton B. Armstrong, Heitor S. Lopes, Carlos R. Erig Lima
    Reconfigurable Computing for Accelerating Protein Folding Simulations. [Citation Graph (0, 0)][DBLP]
    ARC, 2007, pp:314-325 [Conf]
  30. Edson P. Ferlin, Heitor S. Lopes, Carlos R. Erig Lima, Ederson Cichaczewski
    Reconfigurable Parallel Architecture for Genetic Algorithms: Application to the Synthesis of Digital Circuits. [Citation Graph (0, 0)][DBLP]
    ARC, 2007, pp:326-336 [Conf]
  31. Sonia Mota, Eduardo Ros, Javier Díaz, Rafael Rodríguez-Gomez, Richard Carrillo
    A Space Variant Mapping Architecture for Reliable Car Segmentation. [Citation Graph (0, 0)][DBLP]
    ARC, 2007, pp:337-342 [Conf]
  32. Shinya Hiramoto, Masaki Nakanishi, Shigeru Yamashita, Yasuhiko Nakashima
    A Hardware SAT Solver Using Non-chronological Backtracking and Clause Recording Without Overheads. [Citation Graph (0, 0)][DBLP]
    ARC, 2007, pp:343-349 [Conf]
  33. Séamas McGettrick, Dermot Geraghty, Ciarán McElroy
    Searching the Web with an FPGA Based Search Engine. [Citation Graph (0, 0)][DBLP]
    ARC, 2007, pp:350-357 [Conf]
  34. Yoshiki Yamaguchi, Kenji Kanazawa, Yoshiharu Ohke, Tsutomu Maruyama
    An Acceleration Method for Evolutionary Systems Based on Iterated Prisoner's Dilemma. [Citation Graph (0, 0)][DBLP]
    ARC, 2007, pp:358-364 [Conf]
  35. Matteo Tomasi, Javier Díaz, Eduardo Ros
    Real Time Architectures for Moving-Objects Tracking. [Citation Graph (0, 0)][DBLP]
    ARC, 2007, pp:365-372 [Conf]
  36. Patrick Rocke, Brian McGinley, Fearghal Morgan, John Maher
    Reconfigurable Hardware Evolution Platform for a Spiking Neural Network Robotics Controller. [Citation Graph (0, 0)][DBLP]
    ARC, 2007, pp:373-378 [Conf]
  37. Carlos R. Erig Lima, Heitor S. Lopes, Maiko R. Moroz, Ramon M. Menezes
    Multiple Sequence Alignment Using Reconfigurable Computing. [Citation Graph (0, 0)][DBLP]
    ARC, 2007, pp:379-384 [Conf]
  38. Wagner R. Weinert, César Benitez, Heitor S. Lopes, Carlos R. Erig Lima
    Simulation of the Dynamic Behavior of One-Dimensional Cellular Automata Using Reconfigurable Computing. [Citation Graph (0, 0)][DBLP]
    ARC, 2007, pp:385-390 [Conf]
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