Conferences in DBLP
(ets) Rene Segers If It's All about Yield, Why Talk about Testing? [Citation Graph (0, 0)][DBLP ] Conf ] Ben Bennetts Electronics Design-for-Test: Past, Present and Future. [Citation Graph (0, 0)][DBLP ] Conf ] Stefan Holst , Hans-Joachim Wunderlich Adaptive Debug and Diagnosis without Fault Dictionaries. [Citation Graph (0, 0)][DBLP ] Conf ] Alexandre Rousset , Alberto Bosio , Patrick Girard , Christian Landrault , Serge Pravossoudovitch , Arnaud Virazel DERRIC: A Tool for Unified Logic Diagnosis. [Citation Graph (0, 0)][DBLP ] Conf ] Erik Schüler , Marcelo Negreiros , Pascal Nouet , Luigi Carro A Digitally Testable Capacitance-Insensitive Mixed-Signal Filter. [Citation Graph (0, 0)][DBLP ] Conf ] Jaan Raik , Raimund Ubar , Vineeth Govind Test Configurations for Diagnosing Faulty Links in NoC Switches. [Citation Graph (0, 0)][DBLP ] Conf ] Fawnizu Azmadi Hussin , Tomokazu Yoneda , Hideo Fujiwara Optimization of NoC Wrapper Design under Bandwidth and Test Time Constraints. [Citation Graph (0, 0)][DBLP ] Conf ] Ivo Koren , Frank Demmerle , Roland May , Martin Kaibel , Sebastian Sattler FPGA Architecture for RF Transceiver System and Mixed-Signal Low Cost Tests. [Citation Graph (0, 0)][DBLP ] Conf ] Marcelo Negreiros , Luigi Carro , Altamiro Amadeu Susin Digital Generation of Signals for Low Cost RF BIST. [Citation Graph (0, 0)][DBLP ] Conf ] Shaji Krishnan , Rene Jonker , Leon van de Logt Variance Reduction for Supply Ramp Based Cheap RF Test Alternatives. [Citation Graph (0, 0)][DBLP ] Conf ] Tao Xu , Krishnendu Chakrabarty Parallel Scan-Like Testing and Fault Diagnosis Techniques for Digital Microfluidic Biochips. [Citation Graph (0, 0)][DBLP ] Conf ] Bart Vermeulen , Kees Goossens , Remco van Steeden , Martijn T. Bennebroek Communication-Centric SoC Debug Using Transactions. [Citation Graph (0, 0)][DBLP ] Conf ] O. Ginez , Jean Michel Daga , Patrick Girard , Christian Landrault , Serge Pravossoudovitch , Arnaud Virazel Electrical Simulation Model of the 2T-FLOTOX Core-Cell for Defect Injection and Faulty Behavior Prediction in eFlash Memories. [Citation Graph (0, 0)][DBLP ] Conf ] Said Hamdioui , Zaid Al-Ars , Javier Jiménez , Jose Calero PPM Reduction on Embedded Memories in System on Chip. [Citation Graph (0, 0)][DBLP ] Conf ] Philipp Öhler , Sybille Hellebrand , Hans-Joachim Wunderlich An Integrated Built-In Test and Repair Approach for Memories with 2D Redundancy. [Citation Graph (0, 0)][DBLP ] Conf ] A. Ney , Patrick Girard , Christian Landrault , Serge Pravossoudovitch , Arnaud Virazel , Magali Bastian Dynamic Two-Cell Incorrect Read Fault Due to Resistive-Open Defects in the Sense Amplifiers of SRAMs. [Citation Graph (0, 0)][DBLP ] Conf ] N. Dumas , Z. Xu , K. Georgopoulos , R. J. T. Bunyan , A. Richardson A Novel Approach for Online Sensor Testing Based on an Encoded Test Stimulus. [Citation Graph (0, 0)][DBLP ] Conf ] A. Merentitis , Nektarios Kranitis , Antonis M. Paschalis , Dimitris Gizopoulos Selecting Power-Optimal SBST Routines for On-Line Processor Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Tomoo Inoue , Takashi Fujii , Hideyuki Ichihara Optimal Contexts for the Self-Test of Coarse Grain Dynamically Reconfigurable Processors. [Citation Graph (0, 0)][DBLP ] Conf ] Zhanglei Wang , Krishnendu Chakrabarty , Michael Bienek A Seed-Selection Method to Increase Defect Coverage for LFSR-Reseeding-Based Test Compression. [Citation Graph (0, 0)][DBLP ] Conf ] Raimund Ubar , Sergei Devadze , Jaan Raik , Artur Jutman Ultra Fast Parallel Fault Analysis on Structurally Synthesized BDDs. [Citation Graph (0, 0)][DBLP ] Conf ] Rene Krenz-Baath , Andreas Glowatz , Jürgen Schlöffel Computation and Application of Absolute Dominators in Industrial Designs. [Citation Graph (0, 0)][DBLP ] Conf ] Huaxing Tang , Sharma Manish , Janusz Rajski , Martin Keim , Brady Benware Analyzing Volume Diagnosis Results with Statistical Learning for Yield Improvement. [Citation Graph (0, 0)][DBLP ] Conf ] Irith Pomeranz , Sudhakar M. Reddy Diagnostic Test Generation Based on Subsets of Faults. [Citation Graph (0, 0)][DBLP ] Conf ] Luca Sterpone , Massimo Violante Static and Dynamic Analysis of SEU Effects in SRAM-Based FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] C. A. Lisboa , Marcelo Ienczczak Erigson , Luigi Carro System Level Approaches for Mitigation of Long Duration Transient Faults in Future Technologies. [Citation Graph (0, 0)][DBLP ] Conf ] Sankar Gurumurthy , Ramtilak Vemu , Jacob A. Abraham , Daniel G. Saab Automatic Generation of Instructions to Robustly Test Delay Defects in Processors. [Citation Graph (0, 0)][DBLP ] Conf ] Paolo Bernardi , Michelangelo Grosso , E. Sanchez , Matteo Sonza Reorda On the Automatic Generation of Test Programs for Path-Delay Faults in Microprocessor Cores. [Citation Graph (0, 0)][DBLP ] Conf ] Stephen K. Sunter , Aubin Roy Purely Digital BIST for Any PLL or DLL. [Citation Graph (0, 0)][DBLP ] Conf ] Philippe Cauvet , Serge Bernard , Michel Renovell System-in-Package, a Combination of Challenges and Solutions. [Citation Graph (0, 0)][DBLP ] Conf ] Klaus Luther Embedded Tutorial: IC Test Cost Benchmarking. [Citation Graph (0, 0)][DBLP ] Conf ] Peter Maxwell Wafer Level Reliability Screens. [Citation Graph (0, 0)][DBLP ] Conf ] Nicola Nicolici , Xiaoqing Wen Embedded Tutorial on Low Power Test. [Citation Graph (0, 0)][DBLP ] Conf ] Vincent Kerzerho , Philippe Cauvet , Serge Bernard , Florence Azaïs , Mariane Comte , Michel Renovell "Analogue Network of Converters": A DFT Technique to Test a Complete Set of ADCs and DACs Embedded in a Complex SiP or SOC. [Citation Graph (0, 0)][DBLP ] Conf ] 