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Conferences in DBLP

(ets)
2006 (conf/ets/2006)

  1. Robin Saxby
    Innovation and Wealth Creation from Technology. [Citation Graph (0, 0)][DBLP]
    European Test Symposium, 2006, pp:3- [Conf]
  2. Steve Furber
    Living with Failure: Lessons from Nature? [Citation Graph (0, 0)][DBLP]
    European Test Symposium, 2006, pp:4-8 [Conf]
  3. Gefu Xu, Adit D. Singh
    Low Cost Launch-on-Shift Delay Test with Slow Scan Enable. [Citation Graph (0, 0)][DBLP]
    European Test Symposium, 2006, pp:9-14 [Conf]
  4. Noohul Basheer Zain Ali, Mark Zwolinski, Bashir M. Al-Hashimi, Peter Harrod
    Dynamic Voltage Scaling Aware Delay Fault Testing. [Citation Graph (0, 0)][DBLP]
    European Test Symposium, 2006, pp:15-20 [Conf]
  5. Zhuo Zhang, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski, Bashir M. Al-Hashimi
    Enhancing Delay Fault Coverage through Low Power Segmented Scan. [Citation Graph (0, 0)][DBLP]
    European Test Symposium, 2006, pp:21-28 [Conf]
  6. Mohammad Hosseinabady, Pejman Lotfi-Kamran, Giorgio Di Natale, Stefano Di Carlo, Alfredo Benso, Paolo Prinetto
    Single-Event Upset Analysis and Protection in High Speed Circuits. [Citation Graph (0, 0)][DBLP]
    European Test Symposium, 2006, pp:29-34 [Conf]
  7. Maryam Ashouei, Soumendu Bhattacharya, Abhijit Chatterjee
    Improving SNR for DSM Linear Systems Using Probabilistic Error Correction and State Restoration: A Comparative Study. [Citation Graph (0, 0)][DBLP]
    European Test Symposium, 2006, pp:35-42 [Conf]
  8. Gurgen Harutunyan, Valery A. Vardanian, Yervant Zorian
    Minimal March Tests for Dynamic Faults in Random Access Memories. [Citation Graph (0, 0)][DBLP]
    European Test Symposium, 2006, pp:43-48 [Conf]
  9. Alfredo Benso, Alberto Bosio, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto
    A 22n March Test for Realistic Static Linked Faults in SRAMs. [Citation Graph (0, 0)][DBLP]
    European Test Symposium, 2006, pp:49-54 [Conf]
  10. Yu-Jen Huang, Jin-Fu Li
    Testing Active Neighborhood Pattern-Sensitive Faults of Ternary Content Addressable Memories. [Citation Graph (0, 0)][DBLP]
    European Test Symposium, 2006, pp:55-62 [Conf]
  11. Wenjing Rao, Alex Orailoglu, Ramesh Karri
    Fault Identification in Reconfigurable Carry Lookahead Adders Targeting Nanoelectronic Fabrics. [Citation Graph (0, 0)][DBLP]
    European Test Symposium, 2006, pp:63-68 [Conf]
  12. Kentaroh Katoh, Hideo Ito
    Built-In Self-Test for PEs of Coarse Grained Dynamically Reconfigurable Devices. [Citation Graph (0, 0)][DBLP]
    European Test Symposium, 2006, pp:69-74 [Conf]
  13. Matteo Sonza Reorda, Luca Sterpone, Massimo Violante, Marta Portela-García, Celia López-Ongil, Luis Entrena
    Fault Injection-based Reliability Evaluation of SoPCs. [Citation Graph (0, 0)][DBLP]
    European Test Symposium, 2006, pp:75-82 [Conf]
  14. Qiang Xu, Baosheng Wang, F. Y. Young
    Retention-Aware Test Scheduling for BISTed Embedded SRAMs. [Citation Graph (0, 0)][DBLP]
    European Test Symposium, 2006, pp:83-88 [Conf]
  15. Slimane Boutobza, Michael Nicolaidis, Kheiredine M. Lamara, Andrea Costa
    A Transparent based Programmable Memory BIST. [Citation Graph (0, 0)][DBLP]
    European Test Symposium, 2006, pp:89-96 [Conf]
  16. Bernd Laquai, Martin Hua, Guido Schulze, Michael Braun
    A Flexible and Scaleable Methodology for Testing High Speed Source Synchronous Interfaces on ATE with Multiple Fixed Phase Capture and Compare. [Citation Graph (0, 0)][DBLP]
    European Test Symposium, 2006, pp:97-102 [Conf]
  17. Matthew Collins, Bashir M. Al-Hashimi
    On-Chip Time Measurement Architecture with Femtosecond Timing Resolution. [Citation Graph (0, 0)][DBLP]
    European Test Symposium, 2006, pp:103-110 [Conf]
  18. Ramashis Das, Igor L. Markov, John P. Hayes
    On-Chip Test Generation Using Linear Subspaces. [Citation Graph (0, 0)][DBLP]
    European Test Symposium, 2006, pp:111-116 [Conf]
  19. Artur Pogiel, Janusz Rajski, Jerzy Tyszer
    Convolutional Compactors with Variable Polynomials. [Citation Graph (0, 0)][DBLP]
    European Test Symposium, 2006, pp:117-122 [Conf]
  20. Valentin Gherman, Hans-Joachim Wunderlich, Jürgen Schlöffel, Michael Garbers
    Deterministic Logic BIST for Transition Fault Testing. [Citation Graph (0, 0)][DBLP]
    European Test Symposium, 2006, pp:123-130 [Conf]
  21. Gildas Leger, Adoración Rueda
    Experimental Validation of a Fully Digital BISTfor Cascaded Sigma Delta Modulators. [Citation Graph (0, 0)][DBLP]
    European Test Symposium, 2006, pp:131-136 [Conf]
  22. Erik Schüler, Daniel Scain Farenzena, Luigi Carro
    Evaluating Sigma-Delta Modulated Signals to Develop Fault-Tolerant Circuits. [Citation Graph (0, 0)][DBLP]
    European Test Symposium, 2006, pp:137-144 [Conf]
  23. Sandeep Kumar Goel, Maurice Meijer, José Pineda de Gyvez
    Testing and Diagnosis of Power Switches in SOCs. [Citation Graph (0, 0)][DBLP]
    European Test Symposium, 2006, pp:145-150 [Conf]
  24. M. Cimino, H. Lapuyade, M. De Matos, Thierry Taris, Yann Deval, Jean-Baptiste Begueret
    A Robust 130nm-CMOS Built-In Current Sensor Dedicated to RF Applications. [Citation Graph (0, 0)][DBLP]
    European Test Symposium, 2006, pp:151-158 [Conf]
  25. Vincent Kerzerho, Philippe Cauvet, Serge Bernard, Florence Azaïs, Mariane Comte, Michel Renovell
    "Analogue Network of Converters": A DFT Technique to Test a Complete Set of ADCs and DACs Embedded in a Complex SiP or SOC. [Citation Graph (0, 0)][DBLP]
    European Test Symposium, 2006, pp:159-164 [Conf]
  26. Shalabh Goyal, Abhijit Chatterjee, Mike Atia
    Reducing Sampling Clock Jitter to Improve SNR Measurement of A/D Converters in Production Test. [Citation Graph (0, 0)][DBLP]
    European Test Symposium, 2006, pp:165-172 [Conf]
  27. Irith Pomeranz, Sudhakar M. Reddy
    Fault Collapsing for Transition Faults Using Extended Transition Faults. [Citation Graph (0, 0)][DBLP]
    European Test Symposium, 2006, pp:173-178 [Conf]
  28. Giuseppe Di Guglielmo, Franco Fummi, Cristina Marconcini, Graziano Pravadelli
    FATE: a Functional ATPG to Traverse Unstabilized EFSMs. [Citation Graph (0, 0)][DBLP]
    European Test Symposium, 2006, pp:179-184 [Conf]
  29. N. Devtaprasanna, A. Gunda, P. Krishnamurthy, Sudhakar M. Reddy, Irith Pomeranz
    A Unified Method to Detect Transistor Stuck-Open Faults and Transition Delay Faults. [Citation Graph (0, 0)][DBLP]
    European Test Symposium, 2006, pp:185-192 [Conf]
  30. V. Fresnaud, Lilian Bossuet, Dominique Dallet, Serge Bernard, J. M. Janik, B. Agnus, Philippe Cauvet, Ph. Gandy
    A Low Cost Alternative Method for Harmonics Estimation in a BIST Context. [Citation Graph (0, 0)][DBLP]
    European Test Symposium, 2006, pp:193-198 [Conf]
  31. Byoungho Kim, Hongjoong Shin, Ji Hwan (Paul) Chun, Jacob A. Abraham
    Optimized Signature-Based Statistical Alternate Test for Mixed-Signal Performance Parameters. [Citation Graph (0, 0)][DBLP]
    European Test Symposium, 2006, pp:199-204 [Conf]
  32. Donghoon Han, Shalabh Goyal, Soumendu Bhattacharya, Abhijit Chatterjee
    Low Cost Parametric Failure Diagnosis of RF Transceivers. [Citation Graph (0, 0)][DBLP]
    European Test Symposium, 2006, pp:205-212 [Conf]
  33. Alexandre M. Amory, Kees Goossens, Erik Jan Marinissen, Marcelo Lubaszewski, Fernando Moraes
    Wrapper Design for the Reuse of Networks-on-Chip as Test Access Mechanism. [Citation Graph (0, 0)][DBLP]
    European Test Symposium, 2006, pp:213-218 [Conf]
  34. Xuan-Tu Tran, Jean Durupt, François Bertrand, Vincent Beroulle, Chantal Robach
    A DFT Architecture for Asynchronous Networks-on-Chip. [Citation Graph (0, 0)][DBLP]
    European Test Symposium, 2006, pp:219-224 [Conf]
  35. Delong Shang, Alexandre Yakovlev, Frank P. Burns, Fei Xia, Alexandre V. Bystrov
    Low-Cost Online Testing of Asynchronous Handshakes. [Citation Graph (0, 0)][DBLP]
    European Test Symposium, 2006, pp:225-232 [Conf]
  36. Michal Kopec, Tomasz Garbolino, Krzysztof Gucwa, Andrzej Hlawiczka
    Test-per-Clock Detection, Localization and Identification of Interconnect Faults. [Citation Graph (0, 0)][DBLP]
    European Test Symposium, 2006, pp:233-238 [Conf]
  37. Frank Poehl, Jan Rzeha, Matthias Beck, Michael Gössel, Ralf Arnold, Peter Ossimitz
    On-Chip Evaluation, Compensation, and Storage of Scan Diagnosis Data - A Test Time Efficient Scan Diagnosis Architecture. [Citation Graph (0, 0)][DBLP]
    European Test Symposium, 2006, pp:239-246 [Conf]
  38. Tino Heijmen, André Nieuwland
    Soft-Error Rate Testing of Deep-Submicron Integrated Circuits. [Citation Graph (0, 0)][DBLP]
    European Test Symposium, 2006, pp:247-252 [Conf]
  39. Bill Eklow, Ben Bennetts
    New Techniques for Accessing Embedded Instrumentation: IEEE P1687 (IJTAG). [Citation Graph (0, 0)][DBLP]
    European Test Symposium, 2006, pp:253-254 [Conf]
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