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Conferences in DBLP
(nocs)
2007 (conf/nocs/2007)
- William J. Dally
Enabling Technology for On-Chip Interconnection Networks. [Citation Graph (0, 0)][DBLP]
NOCS, 2007, pp:3- [Conf]
- Paul Gratz, Karthikeyan Sankaralingam, Heather Hanson, Premkishore Shivakumar, Robert G. McDonald, Stephen W. Keckler, Doug Burger
Implementation and Evaluation of a Dynamically Routed Processor Operand Network. [Citation Graph (0, 0)][DBLP]
NOCS, 2007, pp:7-17 [Conf]
- Thomas William Ainsworth, Timothy Mark Pinkston
On Characterizing Performance of the Cell Broadband Engine Element Interconnect Bus. [Citation Graph (0, 0)][DBLP]
NOCS, 2007, pp:18-29 [Conf]
- Donghyun Kim, Kwanho Kim, Joo-Young Kim, Seung-Jin Lee, Hoi-Jun Yoo
Solutions for Real Chip Implementation Issues of NoC and Their Application to Memory-Centric NoC. [Citation Graph (0, 0)][DBLP]
NOCS, 2007, pp:30-39 [Conf]
- Jeffrey D. Hoffman, David Arditti Ilitzky, Anthony Chun, Aliaksei Chapyzhenka
Architecture of the Scalable Communications Core. [Citation Graph (0, 0)][DBLP]
NOCS, 2007, pp:40-52 [Conf]
- Assaf Shacham, Keren Bergman, Luca P. Carloni
On the Design of a Photonic Network-on-Chip. [Citation Graph (0, 0)][DBLP]
NOCS, 2007, pp:53-64 [Conf]
- Crescenzo D'Alessandro, Nikolaos Minas, Keith Heron, David Kinniment, Alexandre Yakovlev
NoC Communication Strategies Using Time-to-Digital Conversion. [Citation Graph (0, 0)][DBLP]
NOCS, 2007, pp:65-74 [Conf]
- Shuming Chen, Xiangyuan Liu
A Low-Latency and Low-Power Hybrid Insertion Methodology for Global Interconnects in VDSM Designs. [Citation Graph (0, 0)][DBLP]
NOCS, 2007, pp:75-82 [Conf]
- Ivan Miro Panades, Alain Greiner
Bi-Synchronous FIFO for Synchronous Circuit Communication Well Suited for Network-on-Chip in GALS Architectures. [Citation Graph (0, 0)][DBLP]
NOCS, 2007, pp:83-94 [Conf]
- Kees Goossens, Bart Vermeulen, Remco van Steeden, Martijn T. Bennebroek
Transaction-Based Communication-Centric Debug. [Citation Graph (0, 0)][DBLP]
NOCS, 2007, pp:95-106 [Conf]
- Théodore Marescaux, Erik Brockmeyer, Henk Corporaal
The Impact of Higher Communication Layers on NoC Supported MP-SoCs. [Citation Graph (0, 0)][DBLP]
NOCS, 2007, pp:107-116 [Conf]
- Evgeny Bolotin, Zvika Guz, Israel Cidon, Ran Ginosar, Avinoam Kolodny
The Power of Priority: NoC Based Distributed Cache Coherency. [Citation Graph (0, 0)][DBLP]
NOCS, 2007, pp:117-126 [Conf]
- Dominique Borrione, Amr Helmy, Laurence V. Pierre, Julien Schmaltz
A Generic Model for Formally Verifying NoC Communication Architectures: A Case Study. [Citation Graph (0, 0)][DBLP]
NOCS, 2007, pp:127-136 [Conf]
- Isask'har Walter, Israel Cidon, Ran Ginosar, Avinoam Kolodny
Access Regulation to Hot-Modules in Wormhole NoCs. [Citation Graph (0, 0)][DBLP]
NOCS, 2007, pp:137-148 [Conf]
- Giovanni De Micheli
Design Technologies for Networks on Chips. [Citation Graph (0, 0)][DBLP]
NOCS, 2007, pp:149- [Conf]
- George Michelogiannakis, Dionisios N. Pnevmatikatos, Manolis Katevenis
Approaching Ideal NoC Latency with Pre-Configured Routes. [Citation Graph (0, 0)][DBLP]
NOCS, 2007, pp:153-162 [Conf]
- Arnab Banerjee, Robert Mullins, Simon Moore
A Power and Energy Exploration of Network-on-Chip Architectures. [Citation Graph (0, 0)][DBLP]
NOCS, 2007, pp:163-172 [Conf]
- Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk, K. P. Lam
A Hybrid Analog-Digital Routing Network for NoC Dynamic Routing. [Citation Graph (0, 0)][DBLP]
NOCS, 2007, pp:173-182 [Conf]
- Jose Flich, A. Mejia, Pedro López, José Duato
Region-Based Routing: An Efficient Routing Mechanism to Tackle Unreliable Hardware in Network on Chips. [Citation Graph (0, 0)][DBLP]
NOCS, 2007, pp:183-194 [Conf]
- Stephan Bourduas, Zeljko Zilic
A Hybrid Ring/Mesh Interconnect for Network-on-Chip Using Hierarchical Rings for Global Routing. [Citation Graph (0, 0)][DBLP]
NOCS, 2007, pp:195-204 [Conf]
- Cristian Grecu, André Ivanov, Partha Pratim Pande, Axel Jantsch, Erno Salminen, Ümit Y. Ogras, Radu Marculescu
Towards Open Network-on-Chip Benchmarks. [Citation Graph (0, 0)][DBLP]
NOCS, 2007, pp:205- [Conf]
- Per Badlund, Axel Jantsch
An Analytical Approach for Dimensioning Mixed Traffic Networks. [Citation Graph (0, 0)][DBLP]
NOCS, 2007, pp:215- [Conf]
- Xuan-Tu Tran, Jean Durupt, Yvain Thonnart, François Bertrand, Vincent Beroulle, Chantal Robach
Implementation of a Design-for-Test Architecture for Asynchronous Networks-on-Chip. [Citation Graph (0, 0)][DBLP]
NOCS, 2007, pp:216- [Conf]
- Mikael Millberg, Axel Jantsch
A Study of NoC Exit Strategies. [Citation Graph (0, 0)][DBLP]
NOCS, 2007, pp:217- [Conf]
- Rostislav (Reuven) Dobkin, Ran Ginosar, Israel Cidon
QNoC Asynchronous Router with Dynamic Virtual Channel Allocation. [Citation Graph (0, 0)][DBLP]
NOCS, 2007, pp:218- [Conf]
- Simon Ogg, Enrico Valli, Crescenzo D'Alessandro, Alexandre Yakovlev, Bashir M. Al-Hashimi, Luca Benini
Reducing Interconnect Cost in NoC through Serialized Asynchronous Links. [Citation Graph (0, 0)][DBLP]
NOCS, 2007, pp:219- [Conf]
- Sheng Xu, Ibis Benito, Wayne P. Burleson
Thermal Impacts on NoC Interconnects. [Citation Graph (0, 0)][DBLP]
NOCS, 2007, pp:220- [Conf]
- Jean-Philippe Diguet, Samuel Evain, Romain Vaslin, Guy Gogniat, Emmanuel Juin
NOC-centric Security of Reconfigurable SoC. [Citation Graph (0, 0)][DBLP]
NOCS, 2007, pp:223-232 [Conf]
- Andreas Hansson, Kees Goossens
Trade-offs in the Configuration of a Network on Chip for Multiple Use-Cases. [Citation Graph (0, 0)][DBLP]
NOCS, 2007, pp:233-242 [Conf]
- Zied Marrakchi, Hayder Mrabet, Christian Masson, Habib Mehrez
Mesh of Tree: Unifying Mesh and MFPGA for Better Device Performances. [Citation Graph (0, 0)][DBLP]
NOCS, 2007, pp:243-252 [Conf]
- Roman Gindin, Israel Cidon, Idit Keidar
NoC-Based FPGA: Architecture and Routing. [Citation Graph (0, 0)][DBLP]
NOCS, 2007, pp:253-264 [Conf]
- Drew Wingard
Reflections on 10 Years as a Commercial On-Chip Interconnect Provider. [Citation Graph (0, 0)][DBLP]
NOCS, 2007, pp:265- [Conf]
- Israel Cidon
NoC: Network or Chip? [Citation Graph (0, 0)][DBLP]
NOCS, 2007, pp:269- [Conf]
- Antonio Pullini, Federico Angiolini, Paolo Meloni, David Atienza, Srinivasan Murali, Luigi Raffo, Giovanni De Micheli, Luca Benini
NoC Design and Implementation in 65nm Technology. [Citation Graph (0, 0)][DBLP]
NOCS, 2007, pp:273-282 [Conf]
- Daniel Greenfield, Arnab Banerjee, Jeong-Gun Lee, Simon Moore
Implications of Rent's Rule for NoC Design and Its Fault-Tolerance. [Citation Graph (0, 0)][DBLP]
NOCS, 2007, pp:283-294 [Conf]
- Cedric Koch-Hofer, Marc Renaudin, Yvain Thonnart, Pascal Vivet
ASC, a SystemC Extension for Modeling Asynchronous Systems, and Its Application to an Asynchronous NoC. [Citation Graph (0, 0)][DBLP]
NOCS, 2007, pp:295-306 [Conf]
- Xiang Wu, Tamer Ragheb, Adnan Aziz, Yehia Massoud
Implementing DSP Algorithms with On-Chip Networks. [Citation Graph (0, 0)][DBLP]
NOCS, 2007, pp:307-316 [Conf]
- Wein-Tsung Shen, Chih-Hao Chao, Yu-Kuang Lien, An-Yeu Wu
A New Binomial Mapping and Optimization Algorithm for Reduced-Complexity Mesh-Based On-Chip Network. [Citation Graph (0, 0)][DBLP]
NOCS, 2007, pp:317-322 [Conf]
- Pascal T. Wolkotte, Philip K. F. Hölzenspies, Gerard J. M. Smit
Fast, Accurate and Detailed NoC Simulations. [Citation Graph (0, 0)][DBLP]
NOCS, 2007, pp:323-332 [Conf]
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