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Conferences in DBLP
(fmics)
2006 (conf/fmics/2006)
- Anna Slobodová
Challenges for Formal Verification in Industrial Setting. [Citation Graph (0, 0)][DBLP]
FMICS/PDMC, 2006, pp:1-22 [Conf]
- Lubos Brim
Distributed Verification: Exploring the Power of Raw Computing Power. [Citation Graph (0, 0)][DBLP]
FMICS/PDMC, 2006, pp:23-34 [Conf]
- Kai Lampka, Markus Siegle, Max Walter
An Easy-to-Use, Efficient Tool-Chain to Analyze the Availability of Telecommunication Equipment. [Citation Graph (0, 0)][DBLP]
FMICS/PDMC, 2006, pp:35-50 [Conf]
- Moritz Hammer, Michael Weber
"To Store or Not To Store" Reloaded: Reclaiming Memory on Demand. [Citation Graph (0, 0)][DBLP]
FMICS/PDMC, 2006, pp:51-66 [Conf]
- Hassen Saïdi
Discovering Symmetries. [Citation Graph (0, 0)][DBLP]
FMICS/PDMC, 2006, pp:67-83 [Conf]
- Lubos Brim, Ivana Cerná, Pavel Moravec 0002, Jirí Simsa
On Combining Partial Order Reduction with Fairness Assumptions. [Citation Graph (0, 0)][DBLP]
FMICS/PDMC, 2006, pp:84-99 [Conf]
- C. Helmstetter, Florence Maraninchi, Laurent Maillet-Contoz
Test Coverage for Loose Timing Annotations. [Citation Graph (0, 0)][DBLP]
FMICS/PDMC, 2006, pp:100-115 [Conf]
- Anders Hessel, Paul Pettersson
Model-Based Testing of a WAP Gateway: An Industrial Case-Study. [Citation Graph (0, 0)][DBLP]
FMICS/PDMC, 2006, pp:116-131 [Conf]
- Tim A. C. Willemse
Heuristics for ioco -Based Test-Based Modelling. [Citation Graph (0, 0)][DBLP]
FMICS/PDMC, 2006, pp:132-147 [Conf]
- Ales Smrcka, Vojtech Rehák, Tomás Vojnar, David Safránek, Petr Matousek, Z. Rehák
Verifying VHDL Designs with Multiple Clocks in SMV. [Citation Graph (0, 0)][DBLP]
FMICS/PDMC, 2006, pp:148-164 [Conf]
- Aad Mathijssen, A. Johannes Pretorius
Verified Design of an Automated Parking Garage. [Citation Graph (0, 0)][DBLP]
FMICS/PDMC, 2006, pp:165-180 [Conf]
- Allan Clark, Stephen Gilmore
Evaluating Quality of Service for Service Level Agreements. [Citation Graph (0, 0)][DBLP]
FMICS/PDMC, 2006, pp:181-194 [Conf]
- Pieter J. L. Cuijpers, A. V. Fyukov
Simulation-Based Performance Analysis of a Medical Image-Processing Architecture. [Citation Graph (0, 0)][DBLP]
FMICS/PDMC, 2006, pp:195-210 [Conf]
- Jan Tobias Mühlberg, Gerald Lüttgen
Blasting Linux Code. [Citation Graph (0, 0)][DBLP]
FMICS/PDMC, 2006, pp:211-226 [Conf]
- Indranil Saha, Suman Roy
A Finite State Modeling of AFDX Frame Management Using Spin. [Citation Graph (0, 0)][DBLP]
FMICS/PDMC, 2006, pp:227-243 [Conf]
- Harald Fecher, Jens Schönborn
UML 2.0 State Machines: Complete Formal Semantics Via core state machine. [Citation Graph (0, 0)][DBLP]
FMICS/PDMC, 2006, pp:244-260 [Conf]
- Borzoo Bonakdarpour, Sandeep S. Kulkarni
Automated Incremental Synthesis of Timed Automata. [Citation Graph (0, 0)][DBLP]
FMICS/PDMC, 2006, pp:261-276 [Conf]
- Wenhui Zhang
SAT-Based Verification of LTL Formulas. [Citation Graph (0, 0)][DBLP]
FMICS/PDMC, 2006, pp:277-292 [Conf]
- Ben Krause, Tim Wahls
jmle: A Tool for Executing JML Specifications Via Constraint Programming. [Citation Graph (0, 0)][DBLP]
FMICS/PDMC, 2006, pp:293-296 [Conf]
- Ansgar Fehnker, Ralf Huuck, Patrick Jayet, Michel Lussenburg, Felix Rauch
Goanna - A Static Model Checker. [Citation Graph (0, 0)][DBLP]
FMICS/PDMC, 2006, pp:297-300 [Conf]
- Erika Ábrahám, Tobias Schubert, Bernd Becker, Martin Fränzle, Christian Herde
Parallel SAT Solving in Bounded Model Checking. [Citation Graph (0, 0)][DBLP]
FMICS/PDMC, 2006, pp:301-315 [Conf]
- Jiri Barnat, Pavel Moravec 0002
Parallel Algorithms for Finding SCCs in Implicitly Given Graphs. [Citation Graph (0, 0)][DBLP]
FMICS/PDMC, 2006, pp:316-330 [Conf]
- Jonathan Ezekiel, Gerald Lüttgen, Radu Siminiceanu
Can Saturation Be Parallelised? [Citation Graph (0, 0)][DBLP]
FMICS/PDMC, 2006, pp:331-346 [Conf]
- Christophe Pajault, Jean-François Pradat-Peyre
Distributed Colored Petri Net Model-Checking with Cyclades. [Citation Graph (0, 0)][DBLP]
FMICS/PDMC, 2006, pp:347-361 [Conf]
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