Conferences in DBLP
Architectural Support for the Stream Execution Model on General-Purpose Processors. [Citation Graph (, )][DBLP ] A Flexible Heterogeneous Multi-Core Architecture. [Citation Graph (, )][DBLP ] Improving Performance Isolation on Chip Multiprocessors via an Operating System Scheduler. [Citation Graph (, )][DBLP ] Software-Pipelining on Multi-Core Architectures. [Citation Graph (, )][DBLP ] Speculative Decoupled Software Pipelining. [Citation Graph (, )][DBLP ] Rotating Register Allocation for Enhanced Pipeline Scheduling. [Citation Graph (, )][DBLP ] Unified Architectural Support for Soft-Error Protection or Software Bug Detection. [Citation Graph (, )][DBLP ] Verification-Aware Microprocessor Design. [Citation Graph (, )][DBLP ] I2SEMS: Interconnects-Independent Security Enhanced Shared Memory Multiprocessor Systems. [Citation Graph (, )][DBLP ] Error Detection Using Dynamic Dataflow Verification. [Citation Graph (, )][DBLP ] Extending Object-Oriented Optimizations for Concurrent Programs. [Citation Graph (, )][DBLP ] Language and Virtual Machine Support for Efficient Fine-Grained Futures in Java. [Citation Graph (, )][DBLP ] Call-chain Software Instruction Prefetching in J2EE Server Applications. [Citation Graph (, )][DBLP ] Detecting Change in Program Behavior for Adaptive Optimization. [Citation Graph (, )][DBLP ] Reducing Energy Consumption of On-Chip Networks Through a Hybrid Compiler-Runtime Approach. [Citation Graph (, )][DBLP ] An Energy Efficient Parallel Architecture Using Near Threshold Operation. [Citation Graph (, )][DBLP ] AA-Sort: A New Parallel Sorting Algorithm for Multi-Core SIMD Processors. [Citation Graph (, )][DBLP ] The Fault Tolerant Parallel Algorithm: the Parallel Recomputing Based Failure Recovery. [Citation Graph (, )][DBLP ] Paceline: Improving Single-Thread Performance in Nanoscale CMPs through Core Overclocking. [Citation Graph (, )][DBLP ] Early Register Release for Out-of-Order Processors with RegisterWindows. [Citation Graph (, )][DBLP ] L1 Cache Filtering Through Random Selection of Memory References. [Citation Graph (, )][DBLP ] Effective Management of DRAM Bandwidth in Multicore Processors. [Citation Graph (, )][DBLP ] A Loop Correlation Technique to Improve Performance Auditing. [Citation Graph (, )][DBLP ] Latency Hiding in Multi-Threading and Multi-Processing of Network Applications. [Citation Graph (, )][DBLP ] Introducing Control Flow into Vectorized Code. [Citation Graph (, )][DBLP ] Automatic Correction of Loop Transformations. [Citation Graph (, )][DBLP ] FAME: FAirly MEasuring Multithreaded Architectures. [Citation Graph (, )][DBLP ] CIGAR: Application Partitioning for a CPU/Coprocessor Architecture. [Citation Graph (, )][DBLP ] Using PredictiveModeling for Cross-Program Design Space Exploration in Multicore Systems. [Citation Graph (, )][DBLP ] CacheScouts: Fine-Grain Monitoring of Shared Caches in CMP Platforms. [Citation Graph (, )][DBLP ] Component-Based Lock Allocation. [Citation Graph (, )][DBLP ] JudoSTM: A Dynamic Binary-Rewriting Approach to Software Transactional Memory. [Citation Graph (, )][DBLP ] The OpenTM Transactional Application Programming Interface. [Citation Graph (, )][DBLP ] A Study of a Transactional Parallel Routing Algorithm. [Citation Graph (, )][DBLP ] Ring Prediction for Non-Uniform Cache Architectures. [Citation Graph (, )][DBLP ] Source Level Merging of Independent Programs. [Citation Graph (, )][DBLP ] Studying the impact of synchronization frequency on scheduling tasks with dependencies in heterogeneous systems. [Citation Graph (, )][DBLP ] Fast prototyping of complex Signal and Image Processing applications on SoC using homogenous network of communicating processors. [Citation Graph (, )][DBLP ] Stream Scheduling: A Framework to Manage Bulk Operations in a Memory Hierarchy. [Citation Graph (, )][DBLP ] Studying Compiler-Microarchitecture Interactions through Interval Analysis. [Citation Graph (, )][DBLP ] FastForward for Efficient Pipeline Parallelism. [Citation Graph (, )][DBLP ] The Automatic Transformation of Linked List Data Structures. [Citation Graph (, )][DBLP ] Trace-based Automatic Padding for Locality Improvement with Correlative Data Visualization Interface. [Citation Graph (, )][DBLP ] A New Parallel Gauss-Seidel Method by Iteration Space Alternate Tiling. [Citation Graph (, )][DBLP ] Performance Portable Optimizations for Loops Containing Communication Operations. [Citation Graph (, )][DBLP ] Exploring the Application Behavior Space Using Parameterized Synthetic Benchmarks. [Citation Graph (, )][DBLP ] Studying Asynchronous Shared Memory Computations. [Citation Graph (, )][DBLP ] Fast Track: Supporting Unsafe Optimizations with Software Speculation. [Citation Graph (, )][DBLP ] Hybrid Specialization: A Trade-off Between Static and Dynamic Specialization. [Citation Graph (, )][DBLP ] Rate-Driven Control of Resizable Caches for Highly Threaded SMT Processors. [Citation Graph (, )][DBLP ] Redesigning Parallel Symbolic Computations Packages. [Citation Graph (, )][DBLP ] MLP-Aware Dynamic Cache Partitioning. [Citation Graph (, )][DBLP ] A Lightweight Model for Software Thread-Level Speculation (TLS). [Citation Graph (, )][DBLP ] HelperCore_DB: Exploiting Multicore Technology for Databases. [Citation Graph (, )][DBLP ] Data Structure Exploration of Dynamic Applications. [Citation Graph (, )][DBLP ] Dynamic Cache Placement with Two-level Mapping to Reduce Conflict Misses. [Citation Graph (, )][DBLP ] Runahead Threads: Reducing Resource Contention in SMT Processors. [Citation Graph (, )][DBLP ] Reducing the Impact of Process Variability with Prefetching and Criticality-Based Resource Allocation. [Citation Graph (, )][DBLP ] Drug Design on the Cell BroadBand Engine. [Citation Graph (, )][DBLP ] Bridging Inputs and Program Dynamic Behavior. [Citation Graph (, )][DBLP ] Power-Aware Compiler Controllable Chip Multiprocessor. [Citation Graph (, )][DBLP ] RSTM : A Relaxed Consistency Software Transactional Memory for Multicores. [Citation Graph (, )][DBLP ] VB-MT: Design Issues and Performance of the Validation Buffer Microarchitecture for Multithreaded Processors. [Citation Graph (, )][DBLP ] A Scalable Low Power Store Queue for Large InstructionWindow Processors. [Citation Graph (, )][DBLP ] Adapting to Intermittent Faults in Future Multicore Systems. [Citation Graph (, )][DBLP ] A Phase-Adaptive Approach to Increasing Cache Performance. [Citation Graph (, )][DBLP ] Compiler Optimizations for Fault Tolerance Software Checking. [Citation Graph (, )][DBLP ] Optimizing Bandwidth Constraint through Register Interconnection for Stream Processors. [Citation Graph (, )][DBLP ] 