Conferences in DBLP

International Conference on Parallel Architectures and Compilation Techniques (PACT) (IEEEpact)
2009 (conf/IEEEpact/2009)

1. 
   Adaptive Locks: Combining Transactions and Locks for Efficient Concurrency. [Citation Graph (, )][DBLP]
   
   
2. 
   Anaphase: A Fine-Grain Thread Decomposition Scheme for Speculative Multithreading. [Citation Graph (, )][DBLP]
   
   
3. 
   Characterizing the TLB Behavior of Emerging Parallel Workloads on Chip Multiprocessors. [Citation Graph (, )][DBLP]
   
   
4. 
   Interprocedural Load Elimination for Dynamic Optimization of Parallel Programs. [Citation Graph (, )][DBLP]
   
   
5. 
   Quantifying the Potential of Program Analysis Peripherals. [Citation Graph (, )][DBLP]
   
   
6. 
   Algorithmic Skeletons within an Embedded Domain Specific Language for the CELL Processor. [Citation Graph (, )][DBLP]
   
   
7. 
   A Task-Centric Memory Model for Scalable Accelerator Architectures. [Citation Graph (, )][DBLP]
   
   
8. 
   SHIP: Scalable Hierarchical Power Control for Large-Scale Data Centers. [Citation Graph (, )][DBLP]
   
   
9. 
   Exploring Phase Change Memory and 3D Die-Stacking for Power/Thermal Friendly, Fast and Durable Memory Architectures. [Citation Graph (, )][DBLP]
   
   
10. 
    Core-Selectability in Chip Multiprocessors. [Citation Graph (, )][DBLP]
    
    
11. 
    Chainsaw: Using Binary Matching for Relative Instruction Mix Comparison. [Citation Graph (, )][DBLP]
    
    
12. 
    tm_db: A Generic Debugging Library for Transactional Programs. [Citation Graph (, )][DBLP]
    
    
13. 
    StealthTest: Low Overhead Online Software Testing Using Transactional Memory. [Citation Graph (, )][DBLP]
    
    
14. 
    CPROB: Checkpoint Processing with Opportunistic Minimal Recovery. [Citation Graph (, )][DBLP]
    
    
15. 
    Architecture Support for Improving Bulk Memory Copying and Initialization Performance. [Citation Graph (, )][DBLP]
    
    
16. 
    Oblivious Routing in On-Chip Bandwidth-Adaptive Networks. [Citation Graph (, )][DBLP]
    
    
17. 
    Exploiting Parallelism with Dependence-Aware Scheduling. [Citation Graph (, )][DBLP]
    
    
18. 
    ITCA: Inter-task Conflict-Aware CPU Accounting for CMPs. [Citation Graph (, )][DBLP]
    
    
19. 
    Flextream: Adaptive Compilation of Streaming Applications for Heterogeneous Architectures. [Citation Graph (, )][DBLP]
    
    
20. 
    DDCache: Decoupled and Delegable Cache Data and Metadata. [Citation Graph (, )][DBLP]
    
    
21. 
    Zero-Value Caches: Cancelling Loads that Return Zero. [Citation Graph (, )][DBLP]
    
    
22. 
    Soft-OLP: Improving Hardware Cache Performance through Software-Controlled Object-Level Partitioning. [Citation Graph (, )][DBLP]
    
    
23. 
    Memory Performance and Cache Coherency Effects on an Intel Nehalem Multiprocessor System. [Citation Graph (, )][DBLP]
    
    
24. 
    Automatic Tuning of Discrete Fourier Transforms Driven by Analytical Modeling. [Citation Graph (, )][DBLP]
    
    
25. 
    Analytical Modeling of Pipeline Parallelism. [Citation Graph (, )][DBLP]
    
    
26. 
    FASTM: A Log-based Hardware Transactional Memory with Fast Abort Recovery. [Citation Graph (, )][DBLP]
    
    
27. 
    Improving Signatures by Locality Exploitation for Transactional Memory. [Citation Graph (, )][DBLP]
    
    
28. 
    Mapping Out a Path from Hardware Transactional Memory to Speculative Multithreading. [Citation Graph (, )][DBLP]
    
    
29. 
    Polyhedral-Model Guided Loop-Nest Auto-Vectorization. [Citation Graph (, )][DBLP]
    
    
30. 
    Region Based Structure Layout Optimization by Selective Data Copying. [Citation Graph (, )][DBLP]
    
    
31. 
    Data Layout Transformation for Enhancing Data Locality on NUCA Chip Multiprocessors. [Citation Graph (, )][DBLP]
    
    
32. 
    SOS: A Software-Oriented Distributed Shared Cache Management Approach for Chip Multiprocessors. [Citation Graph (, )][DBLP]
    
    
33. 
    Using Aggressor Thread Information to Improve Shared Cache Management for CMPs. [Citation Graph (, )][DBLP]
    
    
34. 
    Cache Sharing Management for Performance Fairness in Chip Multiprocessors. [Citation Graph (, )][DBLP]