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Conferences in DBLP

International Conference on Application of Concurrency to System Design (acsd)
2009 (conf/acsd/2009)

  1. Biologically-Inspired Massively-Parallel Architectures - Computing Beyond a Million Processors. [Citation Graph (, )][DBLP]

  2. Formal Verification of Lock-Free Algorithms. [Citation Graph (, )][DBLP]

  3. Examining Important Corner Cases: Verification of Interacting Architectural Components in System Designs. [Citation Graph (, )][DBLP]

  4. Teak: A Token-Flow Implementation for the Balsa Language. [Citation Graph (, )][DBLP]

  5. Desynchronizing Synchronous Programs by Modes. [Citation Graph (, )][DBLP]

  6. From Concurrent Multi-clock Programs to Deterministic Asynchronous Implementations. [Citation Graph (, )][DBLP]

  7. Scheduling Synchronous Elastic Designs. [Citation Graph (, )][DBLP]

  8. Saving Space in a Time Efficient Simulation Algorithm. [Citation Graph (, )][DBLP]

  9. Checking pi-Calculus Structural Congruence is Graph Isomorphism Complete. [Citation Graph (, )][DBLP]

  10. Petrifying Operating Guidelines for Services. [Citation Graph (, )][DBLP]

  11. Variants of the Language Based Synthesis Problem for Petri Nets. [Citation Graph (, )][DBLP]

  12. Flat Arbiters. [Citation Graph (, )][DBLP]

  13. Trading Off Concurrency to Generate Behavioral Adapters. [Citation Graph (, )][DBLP]

  14. Why Are Modalities Good for Interface Theories?. [Citation Graph (, )][DBLP]

  15. Model Checking Verilog Descriptions of Cell Libraries. [Citation Graph (, )][DBLP]

  16. Time Arc Petri Nets and Their Analysis. [Citation Graph (, )][DBLP]

  17. Specification Enforcing Refinement for Convertibility Verification. [Citation Graph (, )][DBLP]

  18. Parameterised Process Algebraic Verification by Precongruence Reduction. [Citation Graph (, )][DBLP]

  19. Verifying Deadlock- and Livelock Freedom in an SOA Scenario. [Citation Graph (, )][DBLP]

  20. Genet: A Tool for the Synthesis and Mining of Petri Nets. [Citation Graph (, )][DBLP]

  21. DESIJ--Enabling Decomposition-Based Synthesis of Complex Asynchronous Controllers. [Citation Graph (, )][DBLP]

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