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Conferences in DBLP
A Fast Scheme to Investigate Thermal-Aware Scheduling Policy for Multicore Processors. [Citation Graph (, )][DBLP]
Dealing with Traffic-Area Trade-Off in Direct Coherence Protocols for Many-Core CMPs. [Citation Graph (, )][DBLP]
An Efficient Lightweight Shared Cache Design for Chip Multiprocessors. [Citation Graph (, )][DBLP]
A Novel Cache Organization for Tiled Chip Multiprocessor. [Citation Graph (, )][DBLP]
A Performance Model for Run-Time Reconfigurable Hardware Accelerator. [Citation Graph (, )][DBLP]
SPMTM: A Novel ScratchPad Memory Based Hybrid Nested Transactional Memory Framework. [Citation Graph (, )][DBLP]
Implementation of Rotation Invariant Multi-View Face Detection on FPGA. [Citation Graph (, )][DBLP]
The Design and Evaluation of a Selective Way Based Trace Cache. [Citation Graph (, )][DBLP]
A Fine-Grained Pipelined Implementation for Large-Scale Matrix Inversion on FPGA. [Citation Graph (, )][DBLP]
L1 Collective Cache: Managing Shared Data for Chip Multiprocessors. [Citation Graph (, )][DBLP]
Efficient Multiplication of Polynomials on Graphics Hardware. [Citation Graph (, )][DBLP]
Performance Optimization Strategies of High Performance Computing on GPU. [Citation Graph (, )][DBLP]
A Practical Approach of Curved Ray Prestack Kirchhoff Time Migration on GPGPU. [Citation Graph (, )][DBLP]
GCSim: A GPU-Based Trace-Driven Simulator for Multi-level Cache. [Citation Graph (, )][DBLP]
A Hybrid Parallel Signature Matching Model for Network Security Applications Using SIMD GPU. [Citation Graph (, )][DBLP]
HPVZ: A High Performance Virtual Computing Environment for Super Computers. [Citation Graph (, )][DBLP]
High Performance Support of Lustre over Customized HSNI for HPC. [Citation Graph (, )][DBLP]
ViroLab Security and Virtual Organization Infrastructure. [Citation Graph (, )][DBLP]
E2EDSM: An Edge-to-Edge Data Service Model for Mass Streaming Media Transmission. [Citation Graph (, )][DBLP]
Iso-Level CAFT: How to Tackle the Combination of Communication Overhead Reduction and Fault Tolerance Scheduling. [Citation Graph (, )][DBLP]
MaGate Simulator: A Simulation Environment for a Decentralized Grid Scheduler. [Citation Graph (, )][DBLP]
A Distributed Shared Memory Architecture for Occasionally Connected Mobile Environments. [Citation Graph (, )][DBLP]
Time-Adaptive Vertical Handoff Triggering Methods for Heterogeneous Systems. [Citation Graph (, )][DBLP]
Energy-Saving Topology Control for Heterogeneous Ad Hoc Networks. [Citation Graph (, )][DBLP]
Computational Performance of a Parallelized Three-Dimensional High-Order Spectral Element Toolbox. [Citation Graph (, )][DBLP]
Research on Evaluation of Parallelization on an Embedded Multicore Platform. [Citation Graph (, )][DBLP]
MapReduce-Based Pattern Finding Algorithm Applied in Motif Detection for Prescription Compatibility Network. [Citation Graph (, )][DBLP]
Parallelization of the LEMan Code with MPI and OpenMP. [Citation Graph (, )][DBLP]
The Recursive Dual-Net and Its Applications. [Citation Graph (, )][DBLP]
Parallelization Strategies for Mixed Regular-Irregular Applications on Multicore-Systems. [Citation Graph (, )][DBLP]
Performance Improvement of Multimedia Kernels by Alleviating Overhead Instructions on SIMD Devices. [Citation Graph (, )][DBLP]
Large Matrix Multiplication on a Novel Heterogeneous Parallel DSP Architecture. [Citation Graph (, )][DBLP]
Implementing Fast Packet Filters by Software Pipelining on x86 Processors. [Citation Graph (, )][DBLP]
OSL: Optimized Bulk Synchronous Parallel Skeletons on Distributed Arrays. [Citation Graph (, )][DBLP]
Evaluating SPLASH-2 Applications Using MapReduce. [Citation Graph (, )][DBLP]
MPTD: A Scalable and Flexible Performance Prediction Framework for Parallel Systems. [Citation Graph (, )][DBLP]
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