Conferences in DBLP

Architektur von Rechensystemen (arcs)
2009 (conf/arcs/2009)

1. 
   Life on the Treadmill. [Citation Graph (, )][DBLP]
   
   
2. 
   Key Microarchitectural Innovations for Future Microprocessors. [Citation Graph (, )][DBLP]
   
   
3. 
   The Challenges of Multicore: Information and Mis-Information. [Citation Graph (, )][DBLP]
   
   
4. 
   Extracting Coarse-Grained Pipelined Parallelism Out of Sequential Applications for Parallel Processor Arrays. [Citation Graph (, )][DBLP]
   
   
5. 
   Parallelization Approaches for Hardware Accelerators - Loop Unrolling Versus Loop Partitioning. [Citation Graph (, )][DBLP]
   
   
6. 
   Evaluating Sampling Based Hotspot Detection. [Citation Graph (, )][DBLP]
   
   
7. 
   A Reconfigurable Bloom Filter Architecture for BLASTN. [Citation Graph (, )][DBLP]
   
   
8. 
   SoCWire: A Robust and Fault Tolerant Network-on-Chip Approach for a Dynamic Reconfigurable System-on-Chip in FPGAs. [Citation Graph (, )][DBLP]
   
   
9. 
   A Light-Weight Approach to Dynamical Runtime Linking Supporting Heterogenous, Parallel, and Reconfigurable Architectures. [Citation Graph (, )][DBLP]
   
   
10. 
    Ultra-Fast Downloading of Partial Bitstreams through Ethernet. [Citation Graph (, )][DBLP]
    
    
11. 
    SCOPE - Sensor Mote Configuration and Operation Enhancement. [Citation Graph (, )][DBLP]
    
    
12. 
    Generated Horizontal and Vertical Data Parallel GCA Machines for the N-Body Force Calculation. [Citation Graph (, )][DBLP]
    
    
13. 
    Hybrid Resource Discovery Mechanism in Ad Hoc Grid Using Structured Overlay. [Citation Graph (, )][DBLP]
    
    
14. 
    Marketplace-Oriented Behavior in Semantic Multi-Criteria Decision Making Autonomous Systems. [Citation Graph (, )][DBLP]
    
    
15. 
    Self-organized Parallel Cooperation for Solving Optimization Problems. [Citation Graph (, )][DBLP]
    
    
16. 
    Improving Memory Subsystem Performance Using ViVA: Virtual Vector Architecture. [Citation Graph (, )][DBLP]
    
    
17. 
    An Enhanced DMA Controller in SIMD Processors for Video Applications. [Citation Graph (, )][DBLP]
    
    
18. 
    Cache Controller Design on Ultra Low Leakage Embedded Processors. [Citation Graph (, )][DBLP]
    
    
19. 
    Autonomous DVFS on Supply Islands for Energy-Constrained NoC Communication. [Citation Graph (, )][DBLP]
    
    
20. 
    Energy Management System as an Embedded Service: Saving Energy Consumption of ICT. [Citation Graph (, )][DBLP]
    
    
21. 
    A Garbage Collection Technique for Embedded Multithreaded Multicore Processors. [Citation Graph (, )][DBLP]
    
    
22. 
    Empirical Performance Models for Java Workloads. [Citation Graph (, )][DBLP]
    
    
23. 
    Performance Matching of Hardware Acceleration Engines for Heterogeneous MPSoC Using Modular Performance Analysis. [Citation Graph (, )][DBLP]
    
    
24. 
    Evaluating CMPs and Their Memory Architecture. [Citation Graph (, )][DBLP]