Conferences in DBLP

Architektur von Rechensystemen (arcs)
2010 (conf/arcs/2010)

1. 
   HyVM - Hybrid Virtual Machines - Efficient Use of Future Heterogeneous Chip Multiprocessors. [Citation Graph (, )][DBLP]
   
   
2. 
   How to Enhance a Superscalar Processor to Provide Hard Real-Time Capable In-Order SMT. [Citation Graph (, )][DBLP]
   
   
3. 
   Complexity-Effective Rename Table Design for Rapid Speculation Recovery. [Citation Graph (, )][DBLP]
   
   
4. 
   An Embedded GC Module with Support for Multiple Mutators and Weak References. [Citation Graph (, )][DBLP]
   
   
5. 
   A Hierarchical Distributed Control for Power and Performances Optimization of Embedded Systems. [Citation Graph (, )][DBLP]
   
   
6. 
   Autonomic Workload Management for Multi-core Processor Systems. [Citation Graph (, )][DBLP]
   
   
7. 
   Firefly Flashing Synchronization as Inspiration for Self-synchronization of Walking Robot Gait Patterns Using a Decentralized Robot Control Architecture. [Citation Graph (, )][DBLP]
   
   
8. 
   The JoSchKa System: Organic Job Distribution in Heterogeneous and Unreliable Environments. [Citation Graph (, )][DBLP]
   
   
9. 
   On Deadlocks and Fairness in Self-organizing Resource-Flow Systems. [Citation Graph (, )][DBLP]
   
   
10. 
    Ad-Hoc Information Spread between Mobile Devices: A Case Study in Analytical Modeling of Controlled Self-organization in IT Systems. [Citation Graph (, )][DBLP]
    
    
11. 
    MLP-Aware Instruction Queue Resizing: The Key to Power-Efficient Performance. [Citation Graph (, )][DBLP]
    
    
12. 
    Exploiting Inactive Rename Slots for Detecting Soft Errors. [Citation Graph (, )][DBLP]
    
    
13. 
    Efficient Transaction Nesting in Hardware Transactional Memory. [Citation Graph (, )][DBLP]
    
    
14. 
    Decentralized Energy-Management to Control Smart-Home Architectures. [Citation Graph (, )][DBLP]
    
    
15. 
    EnergySaving Cluster Roll: Power Saving System for Clusters. [Citation Graph (, )][DBLP]
    
    
16. 
    Effect of the Degree of Neighborhood on Resource Discovery in Ad Hoc Grids. [Citation Graph (, )][DBLP]
    
    
17. 
    Compiler-Directed Performance Model Construction for Parallel Programs. [Citation Graph (, )][DBLP]
    
    
18. 
    A Method for Accurate High-Level Performance Evaluation of MPSoC Architectures Using Fine-Grained Generated Traces. [Citation Graph (, )][DBLP]
    
    
19. 
    JetBench: An Open Source Real-time Multiprocessor Benchmark. [Citation Graph (, )][DBLP]
    
    
20. 
    A Tightly Coupled Accelerator Infrastructure for Exact Arithmetics. [Citation Graph (, )][DBLP]
    
    
21. 
    Optimizing Stencil Application on Multi-thread GPU Architecture Using Stream Programming Model. [Citation Graph (, )][DBLP]