Conferences in DBLP

IEEE Symposium on Computer Arithmetic (arith)
1993 (conf/arith/1993)

1. 
   An accurate LNS arithmetic unit using interleaved memory function interpolator. [Citation Graph (, )][DBLP]
   
   
2. 
   An underflow-induced graphics failure solved by SLI arithmetic. [Citation Graph (, )][DBLP]
   
   
3. 
   Complex SLI arithmetic: Representation, algorithms and analysis. [Citation Graph (, )][DBLP]
   
   
4. 
   Combined system-level redundancy and modular arithmetic for fault tolerant digital signal processing. [Citation Graph (, )][DBLP]
   
   
5. 
   Adaptive beamforming using RNS arithmetic. [Citation Graph (, )][DBLP]
   
   
6. 
   Integer mapping architectures for the polynomial ring engine. [Citation Graph (, )][DBLP]
   
   
7. 
   n × n carry-save multipliers without final addition. [Citation Graph (, )][DBLP]
   
   
8. 
   Design of a fast validated dot product operation. [Citation Graph (, )][DBLP]
   
   
9. 
   Multi-parallel convolvers. [Citation Graph (, )][DBLP]
   
   
10. 
    New algorithms and VLSI architectures for SRT division and square root. [Citation Graph (, )][DBLP]
    
    
11. 
    Division with speculation of quotient digits. [Citation Graph (, )][DBLP]
    
    
12. 
    Measuring the accuracy of ROM reciprocal tables. [Citation Graph (, )][DBLP]
    
    
13. 
    Hardware starting approximation for the square root operation. [Citation Graph (, )][DBLP]
    
    
14. 
    Very high radix division with selection by rounding and prescaling. [Citation Graph (, )][DBLP]
    
    
15. 
    Efficient complex matrix transformations with CORDIC. [Citation Graph (, )][DBLP]
    
    
16. 
    Floating point Cordic. [Citation Graph (, )][DBLP]
    
    
17. 
    Exact rounding of certain elementary functions. [Citation Graph (, )][DBLP]
    
    
18. 
    BKM: A new hardware algorithm for complex elementary functions. [Citation Graph (, )][DBLP]
    
    
19. 
    The Gauss machine: A Galois-enhanced quadratic residue number system systolic array. [Citation Graph (, )][DBLP]
    
    
20. 
    A 17 × 69 bit multiply and add unit with redundant binary feedback and single cycle latency. [Citation Graph (, )][DBLP]
    
    
21. 
    The design of a 64-bit integer multiplier/divider unit. [Citation Graph (, )][DBLP]
    
    
22. 
    Comparing several GCD algorithms. [Citation Graph (, )][DBLP]
    
    
23. 
    Fast evaluation of polynomials and inverses of polynomials. [Citation Graph (, )][DBLP]
    
    
24. 
    Algorithms and multi-valued circuits for the multioperand addition in the binary stored-carry number system. [Citation Graph (, )][DBLP]
    
    
25. 
    On digit-recurrence division implementations for field programmable gate arrays. [Citation Graph (, )][DBLP]
    
    
26. 
    Estimating the power consumption of CMOS adders. [Citation Graph (, )][DBLP]
    
    
27. 
    Exploiting trivial and redundant computation. [Citation Graph (, )][DBLP]
    
    
28. 
    Efficient multiprecision floating point multiplication with optimal directional rounding. [Citation Graph (, )][DBLP]
    
    
29. 
    Faster numerical algorithms via exception handling. [Citation Graph (, )][DBLP]
    
    
30. 
    A lazy exact arithmetic. [Citation Graph (, )][DBLP]
    
    
31. 
    Fast implementations of RSA cryptography. [Citation Graph (, )][DBLP]
    
    
32. 
    On squaring and multiplying large integers. [Citation Graph (, )][DBLP]
    
    
33. 
    A modular multiplication algorithm with triangle additions. [Citation Graph (, )][DBLP]
    
    
34. 
    High-radix modular multiplication for cryptosystems. [Citation Graph (, )][DBLP]