Conferences in DBLP

Application-Specific Systems, Architectures, and Processors (asap)
2007 (conf/asap/2007)

1. 
   Parallelizing HMMER for Hardware Acceleration on FPGAs. [Citation Graph (, )][DBLP]
   
   
2. 
   FPGA-Based Efficient Design Approach for Large-Size Two's Complement Squarers. [Citation Graph (, )][DBLP]
   
   
3. 
   A Self-Reconfigurable Implementation of the JPEG Encoder. [Citation Graph (, )][DBLP]
   
   
4. 
   Evaluation of a High-Level-Language Methodology for High-Performance Reconfigurable Computers. [Citation Graph (, )][DBLP]
   
   
5. 
   Windowed FIFOs for FPGA-based Multiprocessor Systems. [Citation Graph (, )][DBLP]
   
   
6. 
   Performance Evaluation of Adaptive Routing Algorithms for achieving Fault Tolerance in NoC Fabrics. [Citation Graph (, )][DBLP]
   
   
7. 
   Transaction Specific Virtual Channel Allocation in QoS Supported On-chip Communication. [Citation Graph (, )][DBLP]
   
   
8. 
   Scalable Multi-FPGA Platform for Networks-On-Chip Emulation. [Citation Graph (, )][DBLP]
   
   
9. 
   Mapping and Topology Customization Approaches for Application-Specific STNoC Designs. [Citation Graph (, )][DBLP]
   
   
10. 
    Performance Evaluation of Probe-Send Fault-tolerant Network-on-chip Router. [Citation Graph (, )][DBLP]
    
    
11. 
    Real-time FPGA-implementation for blue-sky Detection. [Citation Graph (, )][DBLP]
    
    
12. 
    An FPGA Implementation of a Fully Verified Double Precision IEEE Floating-Point Adder. [Citation Graph (, )][DBLP]
    
    
13. 
    Estimating Area Costs of Custom Instructions for FPGA-based Reconfigurable Processors. [Citation Graph (, )][DBLP]
    
    
14. 
    FPGA SAR Processor with Window Memory Accesses. [Citation Graph (, )][DBLP]
    
    
15. 
    The 1D Discrete Cosine Transform For Large Point Sizes Implemented On Reconfigurable Hardware. [Citation Graph (, )][DBLP]
    
    
16. 
    LNS Subtraction Using Novel Cotransformation and/or Interpolation. [Citation Graph (, )][DBLP]
    
    
17. 
    Hardware Design of a Binary Integer Decimal-based IEEE P754 Rounding Unit. [Citation Graph (, )][DBLP]
    
    
18. 
    A Hardware-Oriented Method for Evaluating Complex Polynomials. [Citation Graph (, )][DBLP]
    
    
19. 
    Power6 Decimal Divide. [Citation Graph (, )][DBLP]
    
    
20. 
    Systolic Formulation for Low-Complexity Serial-Parallel Implementation of Unified Finite Field Multiplication over GF(2^m). [Citation Graph (, )][DBLP]
    
    
21. 
    Scheduling Register-Allocated Codes in User-Guided High-Level Synthesis. [Citation Graph (, )][DBLP]
    
    
22. 
    Design Flow of a Dedicated Computer Cluster Customized for a Distributed Genetic Algorithm Application. [Citation Graph (, )][DBLP]
    
    
23. 
    A Compact Fading Channel Simulator Using Timing-Driven Resource Sharing. [Citation Graph (, )][DBLP]
    
    
24. 
    0/1 Knapsack on Hardware: A Complete Solution. [Citation Graph (, )][DBLP]
    
    
25. 
    Automatic Generation and Optimisation of Reconfigurable Financial Monte-Carlo Simulations. [Citation Graph (, )][DBLP]
    
    
26. 
    SIMD Vectorization of Histogram Functions. [Citation Graph (, )][DBLP]
    
    
27. 
    A Run-Time Reconfigurable Fabric for 3D Texture Filtering. [Citation Graph (, )][DBLP]
    
    
28. 
    Reconfigurable Universal Adder. [Citation Graph (, )][DBLP]
    
    
29. 
    A Triplet-based Computer Architecture Supporting Parallel Object Computing. [Citation Graph (, )][DBLP]
    
    
30. 
    The Design of a Novel Object-oriented Processor : OOMIPS. [Citation Graph (, )][DBLP]
    
    
31. 
    Run-Time Error Detection in Polynomial Basis Multiplication Using Linear Codes. [Citation Graph (, )][DBLP]
    
    
32. 
    Customizing Reconfigurable On-Chip Crossbar Scheduler. [Citation Graph (, )][DBLP]
    
    
33. 
    Design and Implementation of an Efficient and Power-Aware Architecture for Skin Segmentation in Color Video Stream. [Citation Graph (, )][DBLP]
    
    
34. 
    Entropy Coding on a Programmable Processor Array for Multimedia SoC. [Citation Graph (, )][DBLP]
    
    
35. 
    Temperature-Aware Submesh Allocation Scheme for Heat Balancing on Chip-Multiprocessors. [Citation Graph (, )][DBLP]
    
    
36. 
    Design and implementation of a surface peak thermal detector algorithm. [Citation Graph (, )][DBLP]
    
    
37. 
    A High-Throughput Programmable Decoder for LDPC Convolutional Codes. [Citation Graph (, )][DBLP]
    
    
38. 
    A Novel Low-Power Motion Estimation Design for H.264. [Citation Graph (, )][DBLP]
    
    
39. 
    Reconfigurable Motion Estimation Architecture for Multi-standard Video Compression. [Citation Graph (, )][DBLP]
    
    
40. 
    An Efficient SIMD Architecture with Parallel Memory for 2D Cosine Transforms of Video Coding. [Citation Graph (, )][DBLP]
    
    
41. 
    Reduced Delay BCD Adder. [Citation Graph (, )][DBLP]
    
    
42. 
    Improving the Throughput of On-line Addition for Data Streams. [Citation Graph (, )][DBLP]
    
    
43. 
    Long Live Small Fan-in Majority Gates Their Reign Looks Like Coming! [Citation Graph (, )][DBLP]
    
    
44. 
    Computing Digit Selection Regions for Digit Recurrences. [Citation Graph (, )][DBLP]
    
    
45. 
    Hardware Acceleration for 3-D Radiation Dose Calculation. [Citation Graph (, )][DBLP]
    
    
46. 
    Evaluation of a Tightly Coupled ASIP / Co-Processor Architecture Used in GNSS Receivers. [Citation Graph (, )][DBLP]
    
    
47. 
    Latency Reduction of Global Traffic in Wormhole-Routed Meshes Using Hierarchical Rings for Global Routing. [Citation Graph (, )][DBLP]
    
    
48. 
    Bridging the Gap between FPGAs and Multi-Processor Architectures: A Video Processing Perspective. [Citation Graph (, )][DBLP]
    
    
49. 
    Two-level tiling for MPSoC architecture. [Citation Graph (, )][DBLP]
    
    
50. 
    Architecture Support for Reconfigurable Multithreaded Processors in Programmable Communication Systems. [Citation Graph (, )][DBLP]
    
    
51. 
    Identification of Application Specific Instructions Based on Sub-Graph Isomorphism Constraints. [Citation Graph (, )][DBLP]
    
    
52. 
    A Retargetable Framework for Automated Discovery of Custom Instructions. [Citation Graph (, )][DBLP]
    
    
53. 
    A Simple Central Processing Unit with Multi-Dimensional Logarithmic Number System Extensions. [Citation Graph (, )][DBLP]
    
    
54. 
    A Phase-Coupled Compiler Backend for a New VLIW Processor Architecture Using Two-step Register Allocation. [Citation Graph (, )][DBLP]
    
    
55. 
    An Application Specific Memory Characterization Technique for Co-processor Accelerators. [Citation Graph (, )][DBLP]
    
    
56. 
    GISP: A Transparent Superpage Support Framework for Linux. [Citation Graph (, )][DBLP]
    
    
57. 
    Methodology and Toolset for ASIP Design and Development Targeting Cryptography-Based Applications. [Citation Graph (, )][DBLP]
    
    
58. 
    A 2-Dimension Force-Directed Scheduling Algorithm for Register-File-Connectivity Clustered VLIW Architecture. [Citation Graph (, )][DBLP]
    
    
59. 
    Graphic processors to speed-up simulations for the design of high performance solar receptors. [Citation Graph (, )][DBLP]
    
    
60. 
    Memory Operation Inclusive Instruction-Set Extensions and Data Path Generation. [Citation Graph (, )][DBLP]
    
    
61. 
    Robust Adders Based on Quantum-Dot Cellular Automata. [Citation Graph (, )][DBLP]
    
    
62. 
    A memcpy Hardware Accelerator Solution for Non Cache-line Aligned Copies. [Citation Graph (, )][DBLP]
    
    
63. 
    A Rapid Prototyping Platform for Wireless Medium Access Control Protocols. [Citation Graph (, )][DBLP]
    
    
64. 
    An Efficient Hardware Support for Control Data Validation. [Citation Graph (, )][DBLP]
    
    
65. 
    ISA Support for Fingerprinting and Erasure Codes. [Citation Graph (, )][DBLP]