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Conferences in DBLP

Application-Specific Systems, Architectures, and Processors (asap)
2008 (conf/asap/2008)


  1. Fast custom instruction identification by convex subgraph enumeration. [Citation Graph (, )][DBLP]


  2. Bit matrix multiplication in commodity processors. [Citation Graph (, )][DBLP]


  3. Synthesis of application accelerators on Runtime Reconfigurable Hardware. [Citation Graph (, )][DBLP]


  4. Floating point multiplication rounding schemes for interval arithmetic. [Citation Graph (, )][DBLP]


  5. Fast multivariate signature generation in hardware: The case of rainbow. [Citation Graph (, )][DBLP]


  6. Fault-tolerant dynamically reconfigurable NoC-based SoC. [Citation Graph (, )][DBLP]


  7. Security processor with quantum key distribution. [Citation Graph (, )][DBLP]


  8. Fully-pipelined efficient architectures for FPGA realization of discrete Hadamard transform. [Citation Graph (, )][DBLP]


  9. Reconfigurable Viterbi decoder on mesh connected multiprocessor architecture. [Citation Graph (, )][DBLP]


  10. Run-time thread sorting to expose data-level parallelism. [Citation Graph (, )][DBLP]


  11. A new high-performance scalable dynamic interconnection for FPGA-based reconfigurable systems. [Citation Graph (, )][DBLP]


  12. Extending the SIMPPL SoC architectural framework to support application-specific architectures on multi-FPGA platforms. [Citation Graph (, )][DBLP]


  13. PERMAP: A performance-aware mapping for application-specific SoCs. [Citation Graph (, )][DBLP]


  14. Low-cost implementations of NTRU for pervasive security. [Citation Graph (, )][DBLP]


  15. On the high-throughput implementation of RIPEMD-160 hash algorithm. [Citation Graph (, )][DBLP]


  16. Zodiac: System architecture implementation for a high-performance Network Security Processor. [Citation Graph (, )][DBLP]


  17. Efficient systolization of cyclic convolution for systolic implementation of sinusoidal transforms. [Citation Graph (, )][DBLP]


  18. Resource efficient generators for the floating-point uniform and exponential distributions. [Citation Graph (, )][DBLP]


  19. Low discrepancy sequences for Monte Carlo simulations on reconfigurable platforms. [Citation Graph (, )][DBLP]


  20. A subsampling pulsed UWB demodulator based on a flexible complex SVD. [Citation Graph (, )][DBLP]


  21. Dynamically reconfigurable regular expression matching architecture. [Citation Graph (, )][DBLP]


  22. An MPSoC architecture for the Multiple Target Tracking application in driver assistant system. [Citation Graph (, )][DBLP]


  23. Managing multi-core soft-error reliability through utility-driven cross domain optimization. [Citation Graph (, )][DBLP]


  24. An efficient implementation of a phase unwrapping kernel on reconfigurable hardware. [Citation Graph (, )][DBLP]


  25. A parallel hardware architecture for connected component labeling based on fast label merging. [Citation Graph (, )][DBLP]


  26. Operation shuffling over cycle boundaries for low energy L0 clustering. [Citation Graph (, )][DBLP]


  27. An efficient digital circuit for implementing Sequence Alignment algorithm in an extended processor. [Citation Graph (, )][DBLP]


  28. Concurrent systolic architecture for high-throughput implementation of 3-dimensional discrete wavelet transform. [Citation Graph (, )][DBLP]


  29. Design space exploration of a cooperative MIMO receiver for reconfigurable architectures. [Citation Graph (, )][DBLP]


  30. Dynamic holographic reconfiguration on a four-context ODRGA. [Citation Graph (, )][DBLP]


  31. FPGA-based hardware accelerator of the heat equation with applications on infrared thermography. [Citation Graph (, )][DBLP]


  32. FPGA based singular value decomposition for image processing applications. [Citation Graph (, )][DBLP]


  33. Accelerating Nussinov RNA secondary structure prediction with systolic arrays on FPGAs. [Citation Graph (, )][DBLP]


  34. A multi-FPGA application-specific architecture for accelerating a floating point Fourier Integral Operator. [Citation Graph (, )][DBLP]


  35. Reconfigurable acceleration of microphone array algorithms for speech enhancement. [Citation Graph (, )][DBLP]


  36. Configurable and scalable high throughput turbo decoder architecture for multiple 4G wireless standards. [Citation Graph (, )][DBLP]


  37. Architecture and VLSI realization of a high-speed programmable decoder for LDPC convolutional codes. [Citation Graph (, )][DBLP]


  38. Buffer allocation for advanced packet segmentation in Network Processors. [Citation Graph (, )][DBLP]


  39. New insights on Ling adders. [Citation Graph (, )][DBLP]


  40. An efficient method for evaluating polynomial and rational function approximations. [Citation Graph (, )][DBLP]


  41. Integer and floating-point constant multipliers for FPGAs. [Citation Graph (, )][DBLP]


  42. Mapping of the AES cryptographic algorithm on a Coarse-Grain reconfigurable array processor. [Citation Graph (, )][DBLP]


  43. RECONNECT: A NoC for polymorphic ASICs using a low overhead single cycle router. [Citation Graph (, )][DBLP]


  44. Loop-oriented metrics for exploring an application-specific architecture design-space. [Citation Graph (, )][DBLP]


  45. Rapid estimation of instruction cache hit rates using loop profiling. [Citation Graph (, )][DBLP]


  46. Reducing power consumption of embedded processors through register file partitioning and compiler support. [Citation Graph (, )][DBLP]


  47. Lightweight DMA management mechanisms for multiprocessors on FPGA. [Citation Graph (, )][DBLP]


  48. Memory copies in multi-level memory systems. [Citation Graph (, )][DBLP]


  49. Architecture of a polymorphic ASIC for interoperability across multi-mode H.264 decoders. [Citation Graph (, )][DBLP]


  50. An FPGA architecture for CABAC decoding in manycore systems. [Citation Graph (, )][DBLP]


  51. Novel approach on lifting-based DWT and IDWT processor with multi-context configuration to support different wavelet filters. [Citation Graph (, )][DBLP]


  52. Throughput-scalable hybrid-pipeline architecture for multilevel lifting 2-D DWT of JPEG 2000 coder. [Citation Graph (, )][DBLP]

NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002