An efficient method for evaluating polynomial and rational function approximations. [Citation Graph (, )][DBLP]
Integer and floating-point constant multipliers for FPGAs. [Citation Graph (, )][DBLP]
Mapping of the AES cryptographic algorithm on a Coarse-Grain reconfigurable array processor. [Citation Graph (, )][DBLP]
RECONNECT: A NoC for polymorphic ASICs using a low overhead single cycle router. [Citation Graph (, )][DBLP]
Loop-oriented metrics for exploring an application-specific architecture design-space. [Citation Graph (, )][DBLP]
Rapid estimation of instruction cache hit rates using loop profiling. [Citation Graph (, )][DBLP]
Reducing power consumption of embedded processors through register file partitioning and compiler support. [Citation Graph (, )][DBLP]
Lightweight DMA management mechanisms for multiprocessors on FPGA. [Citation Graph (, )][DBLP]
Memory copies in multi-level memory systems. [Citation Graph (, )][DBLP]
Architecture of a polymorphic ASIC for interoperability across multi-mode H.264 decoders. [Citation Graph (, )][DBLP]
An FPGA architecture for CABAC decoding in manycore systems. [Citation Graph (, )][DBLP]
Novel approach on lifting-based DWT and IDWT processor with multi-context configuration to support different wavelet filters. [Citation Graph (, )][DBLP]
Throughput-scalable hybrid-pipeline architecture for multilevel lifting 2-D DWT of JPEG 2000 coder. [Citation Graph (, )][DBLP]
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NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP