Conferences in DBLP
A brand new wireless day. [Citation Graph (, )][DBLP ] Variability-driven module selection with joint design time optimization and post-silicon tuning. [Citation Graph (, )][DBLP ] Behavioral synthesis with activating unused flip-flops for reducing glitch power in FPGA. [Citation Graph (, )][DBLP ] A multicycle communication architecture and synthesis flow for Global interconnect Resource Sharing. [Citation Graph (, )][DBLP ] Scheduling with integer time budgeting for low-power optimization. [Citation Graph (, )][DBLP ] REWIRED - Register Write Inhibition by Resource Dedication. [Citation Graph (, )][DBLP ] An efficient performance improvement method utilizing specialized functional units in Behavioral Synthesis. [Citation Graph (, )][DBLP ] Predictive power aware management for embedded mobile devices. [Citation Graph (, )][DBLP ] A dynamic-programming algorithm for reducing the energy consumption of pipelined System-Level streaming applications. [Citation Graph (, )][DBLP ] Temperature-aware MPSoC scheduling for reducing hot spots and gradients. [Citation Graph (, )][DBLP ] Run-time power gating of on-chip routers using look-ahead routing. [Citation Graph (, )][DBLP ] Automated techniques for energy efficient scheduling on homogeneous and heterogeneous chip multi-processor architectures. [Citation Graph (, )][DBLP ] Statistical power profile correlation for realistic thermal estimation. [Citation Graph (, )][DBLP ] Reconfigurable RTD-based circuit elements of complete logic functionality. [Citation Graph (, )][DBLP ] MBARC: A scalable memory based reconfigurable computing framework for nanoscale devices. [Citation Graph (, )][DBLP ] Moving forward: A non-search based synthesis method toward efficient CNOT-based quantum circuit synthesis algorithms. [Citation Graph (, )][DBLP ] A CAD tool for RF MEMS devices. [Citation Graph (, )][DBLP ] A 1.2GHz delayed clock generator for high-speed microprocessors. [Citation Graph (, )][DBLP ] LVDS-type on-chip transmision line interconnect with passive equalizers in 90nm CMOS process. [Citation Graph (, )][DBLP ] A slew-rate controlled output driver with one-cycle tuning time. [Citation Graph (, )][DBLP ] A low-leakage current power 180-nm CMOS SRAM. [Citation Graph (, )][DBLP ] A CMOS direct sampling mixer using Switched Capacitor Filter technique for software-defined radio. [Citation Graph (, )][DBLP ] Small-area CMOS RF distributed mixer using multi-port inductors. [Citation Graph (, )][DBLP ] Dynamic supply noise measurement circuit composed of standard cells suitable for in-site SoC power integrity verification. [Citation Graph (, )][DBLP ] Duo-binary circular turbo decoder based on border metric encoding for WiMAX. [Citation Graph (, )][DBLP ] Area and power efficient design of coarse time synchronizer and frequency offset estimator for fixed WiMAX systems. [Citation Graph (, )][DBLP ] A low-cost cryptographic processor for security embedded system. [Citation Graph (, )][DBLP ] Multithreaded coprocessor interface for multi-core multimedia SoC. [Citation Graph (, )][DBLP ] Parameterized embedded in-circuit emulator and its retargetable debugging software for microprocessor/microcontroller/DSP processor. [Citation Graph (, )][DBLP ] Global optimization of common subexpressions for multiplierless synthesis of multiple constant multiplications. [Citation Graph (, )][DBLP ] Decomposition based approach for synthesis of multi-level threshold logic circuits. [Citation Graph (, )][DBLP ] Timing-power optimization for mixed-radix Ling adders by integer linear programming. [Citation Graph (, )][DBLP ] Efficient synthesis of compressor trees on FPGAs. [Citation Graph (, )][DBLP ] Area recovery under depth constraint by Cut Substitution for technology mapping for LUT-based FPGAs. [Citation Graph (, )][DBLP ] An optimal algorithm for sizing sequential circuits for industrial library based designs. [Citation Graph (, )][DBLP ] Efficient numerical modeling of random rough surface effects for interconnect internal impedance extraction. [Citation Graph (, )][DBLP ] Efficient techniques for 3-D impedance extraction using mixed boundary element method. [Citation Graph (, )][DBLP ] Generating stable and sparse reluctance/inductance matrix under insufficient conditions. [Citation Graph (, )][DBLP ] Hierarchical Krylov subspace reduced order modeling of large RLC circuits. [Citation Graph (, )][DBLP ] Statistical noise margin estimation for sub-threshold combinational circuits. [Citation Graph (, )][DBLP ] Symmetry-aware placement with transitive closure graphs for analog layout design. [Citation Graph (, )][DBLP ] Constraint-free analog placement with topological symmetry structure. [Citation Graph (, )][DBLP ] TCG-based multi-bend bus driven floorplanning. [Citation Graph (, )][DBLP ] Large-scale fixed-outline floorplanning design using convex optimization techniques. [Citation Graph (, )][DBLP ] Bus-aware microarchitectural floorplanning. [Citation Graph (, )][DBLP ] LP based white space redistribution for thermal via planning and performance optimization in 3D ICs. [Citation Graph (, )][DBLP ] Predictive models and CAD methodology for pattern dependent variability. [Citation Graph (, )][DBLP ] Technology modeling and characterization beyond the 45nm node. [Citation Graph (, )][DBLP ] Synergistic physical synthesis for manufacturability and variability in 45nm designs and beyond. [Citation Graph (, )][DBLP ] MaizeRouter: Engineering an effective global router. [Citation Graph (, )][DBLP ] A new global router for modern designs. [Citation Graph (, )][DBLP ] Routability driven modification method of monotonic via assignment for 2-layer Ball Grid Array packages. [Citation Graph (, )][DBLP ] Ordered escape routing based on Boolean satisfiability. [Citation Graph (, )][DBLP ] MeshWorks: An efficient framework for planning, synthesis and optimization of clock mesh networks. [Citation Graph (, )][DBLP ] Interconnect modeling for improved system-level design optimization. [Citation Graph (, )][DBLP ] NoCOUT : NoC topology generation with mixed packet-switched and point-to-point networks. [Citation Graph (, )][DBLP ] Automatic generation of hardware dependent software for MPSoCs from abstract system specifications. [Citation Graph (, )][DBLP ] Application-specific Network-on-Chip architecture synthesis based on set partitions and Steiner Trees. [Citation Graph (, )][DBLP ] Floating-point reconfiguration array processor for 3D graphics physics engine. [Citation Graph (, )][DBLP ] Super-K: A SoC for single-chip ultra mobile computer. [Citation Graph (, )][DBLP ] The evolution of SoC platform according to the new mobile paradigm. [Citation Graph (, )][DBLP ] Statistical gate delay model for Multiple Input Switching. [Citation Graph (, )][DBLP ] Non-Gaussian Statistical Timing models of die-to-die and within-die parameter variations for full chip analysis. [Citation Graph (, )][DBLP ] Non-Gaussian statistical timing analysis using second-order polynomial fitting. [Citation Graph (, )][DBLP ] A capacitive boosted buffer technique for high-speed process-variation-tolerant interconnect in UDVS application. [Citation Graph (, )][DBLP ] Static timing: Back to our roots. [Citation Graph (, )][DBLP ] Synthesis and design of parameter extractors for low-power pre-computation-based content-addressable memory using gate-block selection algorithm. [Citation Graph (, )][DBLP ] Block cache for embedded systems. [Citation Graph (, )][DBLP ] A Compiler-in-the-Loop framework to explore Horizontally Partitioned Cache architectures. [Citation Graph (, )][DBLP ] Fast, quasi-optimal, and pipelined instruction-set extensions. [Citation Graph (, )][DBLP ] Load scheduling: Reducing pressure on distributed register files for free. [Citation Graph (, )][DBLP ] DPlace2.0: A stable and efficient analytical placement based on diffusion. [Citation Graph (, )][DBLP ] Total power optimization combining placement, sizing and multi-Vt through slack distribution management. [Citation Graph (, )][DBLP ] An innovative Steiner tree based approach for polygon partitioning. [Citation Graph (, )][DBLP ] An MILP-based wire spreading algorithm for PSM-aware layout modification. [Citation Graph (, )][DBLP ] Low power clock buffer planning methodology in F-D placement for large scale circuit design. [Citation Graph (, )][DBLP ] Power grid analysis benchmarks. [Citation Graph (, )][DBLP ] In-band mobile digital TV transmission technology for advanced television systems committee. [Citation Graph (, )][DBLP ] In-vehicle vision processors for driver assistance systems. [Citation Graph (, )][DBLP ] Multi-core DSP for base stations: Large and small. [Citation Graph (, )][DBLP ] 1-cc computer using UWB-IR for wireless sensor network. [Citation Graph (, )][DBLP ] Verifying full-custom multipliers by Boolean equivalence checking and an arithmetic bit level proof. [Citation Graph (, )][DBLP ] A symbolic approach for mixed-signal model checking. [Citation Graph (, )][DBLP ] Faster projection based methods for circuit level verification. [Citation Graph (, )][DBLP ] A debug probe for concurrently debugging multiple embedded cores and inter-core transactions in NoC-based systems. [Citation Graph (, )][DBLP ] A fast two-pass HDL simulation with on-demand dump. [Citation Graph (, )][DBLP ] Hybrid solid-state disks: Combining heterogeneous NAND flash in large SSDs. [Citation Graph (, )][DBLP ] Enabling run-time memory data transfer optimizations at the system level with automated extraction of embedded software metadata information. [Citation Graph (, )][DBLP ] Automatic re-coding of reference code into structured and analyzable SoC models. [Citation Graph (, )][DBLP ] Action coverage formulation for power optimization in body sensor networks. [Citation Graph (, )][DBLP ] Dynamic scheduling of imprecise-computation tasks in maximizing QoS under energy constraints for embedded systems. [Citation Graph (, )][DBLP ] Architecture-level thermal behavioral characterization for multi-core microprocessors. [Citation Graph (, )][DBLP ] Full-chip thermal analysis for the early design stage via generalized integral transforms. [Citation Graph (, )][DBLP ] A stochastic local hot spot alerting technique. [Citation Graph (, )][DBLP ] Design rule optimization of regular layout for leakage reduction in nanoscale design. [Citation Graph (, )][DBLP ] Investigation of diffusion rounding for post-lithography analysis. [Citation Graph (, )][DBLP ] Pessimism reduction in coupling-aware static timing analysis using timing and logic filtering. [Citation Graph (, )][DBLP ] A fast incremental clock skew scheduling algorithm for slack optimization. [Citation Graph (, )][DBLP ] Clock tree synthesis with data-path sensitivity matching. [Citation Graph (, )][DBLP ] Buffered clock tree synthesis for 3D ICs under thermal variations. [Citation Graph (, )][DBLP ] A delay model for interconnect trees based on ABCD matrix. [Citation Graph (, )][DBLP ] Analytical model for the impact of multiple input switching noise on timing. [Citation Graph (, )][DBLP ] Determination of optimal polynomial regression function to decompose on-die systematic and random variations. [Citation Graph (, )][DBLP ] Within-die process variations: How accurately can they be statistically modeled? [Citation Graph (, )][DBLP ] Chebyshev Affine Arithmetic based parametric yield prediction under limited descriptions of uncertainty. [Citation Graph (, )][DBLP ] Distribution arithmetic for stochastical analysis. [Citation Graph (, )][DBLP ] Handling partial correlations in yield prediction. [Citation Graph (, )][DBLP ] Reliability-aware design for nanometer-scale devices. [Citation Graph (, )][DBLP ] An industrial perspective of power-aware reliable SoC design. [Citation Graph (, )][DBLP ] The future of semiconductor industry - A foundry's perspective. [Citation Graph (, )][DBLP ] Soft error rate reduction using redundancy addition and removal. [Citation Graph (, )][DBLP ] Localized random access scan: Towards low area and routing overhead. [Citation Graph (, )][DBLP ] A design- for-diagnosis technique for diagnosing both scan chain faults and combinational circuit faults. [Citation Graph (, )][DBLP ] GECOM: Test data compression combined with all unknown response masking. [Citation Graph (, )][DBLP ] Mixed integer linear programming-based optimal topology synthesis of cascaded crossbar switches. [Citation Graph (, )][DBLP ] Automatic interface synthesis based on the classification of interface protocols of IPs. [Citation Graph (, )][DBLP ] The Shining embedded system design methodology based on self dynamic reconfigurable architectures. [Citation Graph (, )][DBLP ] Robust on-chip bus architecture synthesis for MPSoCs under random tasks arrival. [Citation Graph (, )][DBLP ] A Multi-Processor NoC platform applied on the 802.11i TKIP cryptosystem. [Citation Graph (, )][DBLP ] A unified methodology for power supply noise reduction in modern microarchitecture design. [Citation Graph (, )][DBLP ] Heuristic power/ground network and floorplan co-design method. [Citation Graph (, )][DBLP ] Vertical via design techniques for multi-layered P/G networks. [Citation Graph (, )][DBLP ] Statistical mixed Vt allocation of body-biased circuits for reduced leakage variation. [Citation Graph (, )][DBLP ] Exploring high-speed low-power hybrid arithmetic units at scaled supply and adaptive clock-stretching. [Citation Graph (, )][DBLP ] Circuit lines for guiding the generation of random test sequences for synchronous sequential circuits. [Citation Graph (, )][DBLP ] A new low energy BIST using a statistical code. [Citation Graph (, )][DBLP ] On reducing both shift and capture power for scan-based testing. [Citation Graph (, )][DBLP ] Robust test generation for power supply noise induced path delay faults. [Citation Graph (, )][DBLP ] Test vector chains for increased targeted and untargeted fault coverage. [Citation Graph (, )][DBLP ] Parallel fault backtracing for calculation of fault coverage. [Citation Graph (, )][DBLP ] ReSP: A non-intrusive Transaction-Level Reflective MPSoC Simulation Platform for design space exploration. [Citation Graph (, )][DBLP ] Collaborative hardware/software partition of coarse-grained reconfigurable system using evolutionary ant colony optimization. [Citation Graph (, )][DBLP ] Design space exploration for a coarse grain accelerator. [Citation Graph (, )][DBLP ] Efficient symbolic multi-objective design space exploration. [Citation Graph (, )][DBLP ] Scalable unified dual-radix architecture for Montgomery multiplication in GF(P) and GF(2n ). [Citation Graph (, )][DBLP ] Optimal allocation and placement of thermal sensors for reconfigurable systems and its practical extension. [Citation Graph (, )][DBLP ] Exploring power management in multi-core systems. [Citation Graph (, )][DBLP ] Dependability, power, and performance trade-off on a multicore processor. [Citation Graph (, )][DBLP ] High performance current-mode differential logic. [Citation Graph (, )][DBLP ] NBTI induced performance degradation in logic and memory circuits: how effectively can we approach a reliability solution? [Citation Graph (, )][DBLP ] Reaching the limits of low power design. [Citation Graph (, )][DBLP ] Software-cooperative power-efficient heterogeneous multi-core for media processing. [Citation Graph (, )][DBLP ] Experiences of low power design implementation and verification. [Citation Graph (, )][DBLP ] Low power architecture and design techniques for mobile handset LSI MedityTM M2. [Citation Graph (, )][DBLP ] An efficient, fully nonlinear, variability-aware non-monte-carlo yield estimation procedure with applications to SRAM cells and ring oscillators. [Citation Graph (, )][DBLP ] Analog circuit simulation using range arithmetics. [Citation Graph (, )][DBLP ] LTCC spiral inductor modeling, synthesis, and optimization. [Citation Graph (, )][DBLP ] Symmetry constraint based on mismatch analysis for analog layout in SOI technology. [Citation Graph (, )][DBLP ] SPKM : A novel graph drawing based algorithm for application mapping onto coarse-grained reconfigurable architectures. [Citation Graph (, )][DBLP ] Block remap with turnoff: A variation-tolerant cache design technique. [Citation Graph (, )][DBLP ] ORB: An on-chip optical ring bus communication architecture for multi-processor systems-on-chip. [Citation Graph (, )][DBLP ] Webpage-based benchmarks for mobile device design. [Citation Graph (, )][DBLP ] Panel: Best ways to use billions of devices on a chip. [Citation Graph (, )][DBLP ] VEBoC: Variation and error-aware design for billions of devices on a chip. [Citation Graph (, )][DBLP ] Quo vadis, BTSoC (Billion Transistor SoC)? [Citation Graph (, )][DBLP ] Best ways to use billions of devices on a wireless mobile SoC. [Citation Graph (, )][DBLP ] Best ways to use billions of devices on a chip - Error predictive, defect tolerant and error recovery designs. [Citation Graph (, )][DBLP ] 