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Conferences in DBLP

Asian Test Symposium (ats)
2009 (conf/ats/2009)

  1. CA Based Built-In Self-Test Structure for SoC. [Citation Graph (, )][DBLP]

  2. A Random Jitter RMS Estimation Technique for BIST Applications. [Citation Graph (, )][DBLP]

  3. A Novel Seed Selection Algorithm for Test Time Reduction in BIST. [Citation Graph (, )][DBLP]

  4. Logic BIST Architecture for System-Level Test and Diagnosis. [Citation Graph (, )][DBLP]

  5. Fault Diagnosis under Transparent-Scan. [Citation Graph (, )][DBLP]

  6. Scan Chain Diagnosis by Adaptive Signal Profiling with Manufacturing ATPG Patterns. [Citation Graph (, )][DBLP]

  7. On Improving Diagnostic Test Generation for Scan Chain Failures. [Citation Graph (, )][DBLP]

  8. On Scan Chain Diagnosis for Intermittent Faults. [Citation Graph (, )][DBLP]

  9. Design-for-Test Circuit for the Reduced Code Based Linearity Test Method in Pipelined ADCs with Digital Error Correction Technique. [Citation Graph (, )][DBLP]

  10. Multi-tone Testing of Linear and Nonlinear Analog Circuits Using Polynomial Coefficients. [Citation Graph (, )][DBLP]

  11. Low Cost Dynamic Test Methodology for High Precision ΣD ADCs. [Citation Graph (, )][DBLP]

  12. Very-Low-Voltage Testing of Amorphous Silicon TFT Circuits. [Citation Graph (, )][DBLP]

  13. Scan Compression Implementation in Industrial Design - Case Study. [Citation Graph (, )][DBLP]

  14. Calibration as a Functional Test: An ADC Case Study. [Citation Graph (, )][DBLP]

  15. Customized Algorithms for High Performance Memory Test in Advanced Technology Node. [Citation Graph (, )][DBLP]

  16. A Practical DFT Approach for Complex Low Power Designs. [Citation Graph (, )][DBLP]

  17. DFT Challenges in Next Generation Multi-media IP. [Citation Graph (, )][DBLP]

  18. Yield Ramp up by Scan Chain Diagnosis. [Citation Graph (, )][DBLP]

  19. CAT: A Critical-Area-Targeted Test Set Modification Scheme for Reducing Launch Switching Activity in At-Speed Scan Testing. [Citation Graph (, )][DBLP]

  20. New Scheme of Reducing Shift and Capture Power Using the X-Filling Methodology. [Citation Graph (, )][DBLP]

  21. Deterministic Built-In Self-Test Using Multiple Linear Feedback Shift Registers for Low-Power Scan Testing. [Citation Graph (, )][DBLP]

  22. Low Overhead Time-Multiplexed Online Checking: A Case Study of An H.264 Decoder. [Citation Graph (, )][DBLP]

  23. A FPGA-Based Reconfigurable Software Architecture for Highly Dependable Systems. [Citation Graph (, )][DBLP]

  24. Using Non-trivial Logic Implications for Trace Buffer-Based Silicon Debug. [Citation Graph (, )][DBLP]

  25. A Post-Silicon Debug Support Using High-Level Design Description. [Citation Graph (, )][DBLP]

  26. A Low Overhead On-Chip Path Delay Measurement Circuit. [Citation Graph (, )][DBLP]

  27. An Adaptive Test for Parametric Faults Based on Statistical Timing Information. [Citation Graph (, )][DBLP]

  28. A Delay Measurement Technique Using Signature Registers. [Citation Graph (, )][DBLP]

  29. Functional Built-In Delay Binning and Calibration Mechanism for On-Chip at-Speed Self Test. [Citation Graph (, )][DBLP]

  30. A Practical Approach to Threshold Test Generation for Error Tolerant Circuits. [Citation Graph (, )][DBLP]

  31. Speeding up SAT-Based ATPG Using Dynamic Clause Activation. [Citation Graph (, )][DBLP]

  32. N-distinguishing Tests for Enhanced Defect Diagnosis. [Citation Graph (, )][DBLP]

  33. Dynamic Compaction in SAT-Based ATPG. [Citation Graph (, )][DBLP]

  34. SIRUP: Switch Insertion in RedUndant Pipeline Structures for Yield and Yield/Area Improvement. [Citation Graph (, )][DBLP]

  35. Transaction Level Modeling and Design Space Exploration for SOC Test Architectures. [Citation Graph (, )][DBLP]

  36. Efficient Software-Based Self-Test Methods for Embedded Digital Signal Processors. [Citation Graph (, )][DBLP]

  37. Is Low Power Testing Necessary? What does the Test Industry Truly Need?. [Citation Graph (, )][DBLP]

  38. A Scalable Scan Architecture for Godson-3 Multicore Microprocessor. [Citation Graph (, )][DBLP]

  39. Kiss the Scan Goodbye: A Non-scan Architecture for High Coverage, Low Test Data Volume and Low Test Application Time. [Citation Graph (, )][DBLP]

  40. Multiple Scan Trees Synthesis for Test Time/Data and Routing Length Reduction under Output Constraint. [Citation Graph (, )][DBLP]

  41. Leveraging Partially Enhanced Scan for Improved Observability in Delay Fault Testing. [Citation Graph (, )][DBLP]

  42. BIST Driven Power Conscious Post-Manufacture Tuning of Wireless Transceiver Systems Using Hardware-Iterated Gradient Search. [Citation Graph (, )][DBLP]

  43. Self-Calibrating Embedded RF Down-Conversion Mixers. [Citation Graph (, )][DBLP]

  44. A BIST Solution for the Functional Characterization of RF Systems Based on Envelope Response Analysis. [Citation Graph (, )][DBLP]

  45. Exploiting Zero-Crossing for the Analysis of FM Modulated Analog/RF Signals Using Digital ATE. [Citation Graph (, )][DBLP]

  46. IEEE 1500 Compatible Interconnect Test with Maximal Test Concurrency. [Citation Graph (, )][DBLP]

  47. Multiple-Core under Test Architecture for HOY Wireless Testing Platform. [Citation Graph (, )][DBLP]

  48. Partition Based SoC Test Scheduling with Thermal and Power Constraints under Deep Submicron Technologies. [Citation Graph (, )][DBLP]

  49. Test Integration for SOC Supporting Very Low-Cost Testers. [Citation Graph (, )][DBLP]

  50. Why is Conventional ATPG Not Sufficient for Advanced Low Power Designs?. [Citation Graph (, )][DBLP]

  51. New Class of Tests for Open Faults with Considering Adjacent Lines. [Citation Graph (, )][DBLP]

  52. Test Pattern Selection and Customization Targeting Reduced Dynamic and Leakage Power Consumption. [Citation Graph (, )][DBLP]

  53. Deterministic Algorithms for ATPG under Leakage Constraints. [Citation Graph (, )][DBLP]

  54. Extended Selective Encoding of Scan Slices for Reducing Test Data and Test Power. [Citation Graph (, )][DBLP]

  55. A Multi-dimensional Pattern Run-Length Method for Test Data Compression. [Citation Graph (, )][DBLP]

  56. Bit-Operation-Based Seed Augmentation for LFSR Reseeding with High Defect Coverage. [Citation Graph (, )][DBLP]

  57. Testing Embedded Memories in the Nano-Era: Will the Existing Approaches Survive?. [Citation Graph (, )][DBLP]

  58. A Non-Intrusive and Accurate Inspection Method for Segment Delay Variabilities. [Citation Graph (, )][DBLP]

  59. Bridging Fault Diagnosis to Identify the Layer of Systematic Defects. [Citation Graph (, )][DBLP]

  60. Delay Fault Diagnosis in Sequential Circuits. [Citation Graph (, )][DBLP]

  61. A Partially-Exhaustive Gate Transition Fault Model. [Citation Graph (, )][DBLP]

  62. An On-Chip Integrator Leakage Characterization Technique and Its Application to Switched Capacitor Circuits Testing. [Citation Graph (, )][DBLP]

  63. LFSR-Based Performance Characterization of Nonlinear Analog and Mixed-Signal Circuits. [Citation Graph (, )][DBLP]

  64. A Jitter Characterizing BIST with Pulse-Amplifying Technique. [Citation Graph (, )][DBLP]

  65. A Low-Cost Output Response Analyzer for the Built-in-Self-Test S-? Modulator Based on the Controlled Sine Wave Fitting Method. [Citation Graph (, )][DBLP]

  66. New Algorithms for Address Decoder Delay Faults and Bit Line Imbalance Faults. [Citation Graph (, )][DBLP]

  67. Testability Exploration of 3-D RAMs and CAMs. [Citation Graph (, )][DBLP]

  68. Fault Diagnosis Using Test Primitives in Random Access Memories. [Citation Graph (, )][DBLP]

  69. Test Generation for Designs with On-Chip Clock Generators. [Citation Graph (, )][DBLP]

  70. On the Generation of Functional Test Programs for the Cache Replacement Logic. [Citation Graph (, )][DBLP]

  71. Compact Test Generation for Small-Delay Defects Using Testable-Path Information. [Citation Graph (, )][DBLP]

  72. At-Speed Scan Test Method for the Timing Optimization and Calibration. [Citation Graph (, )][DBLP]

  73. M-IVC: Using Multiple Input Vectors to Minimize Aging-Induced Delay. [Citation Graph (, )][DBLP]

  74. Analysis of Resistive Bridging Defects in a Synchronizer. [Citation Graph (, )][DBLP]

  75. On-Chip TSV Testing for 3D IC before Bonding Using Sense Amplification. [Citation Graph (, )][DBLP]

  76. Test Pattern Selection for Potentially Harmful Open Defects in Power Distribution Networks. [Citation Graph (, )][DBLP]

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