The SCEAS System
Navigation Menu

Conferences in DBLP

International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES) (cases)
2008 (conf/cases/2008)

  1. StageNetSlice: a reconfigurable microarchitecture building block for resilient CMP systems. [Citation Graph (, )][DBLP]

  2. A light-weight cache-based fault detection and checkpointing scheme for MPSoCs enabling relaxed execution synchronization. [Citation Graph (, )][DBLP]

  3. ZebraNet and beyond: applications and systems support for mobile, dynamic networks. [Citation Graph (, )][DBLP]

  4. Non-intrusive dynamic application profiler for detailed loop execution characterization. [Citation Graph (, )][DBLP]

  5. Exploring and predicting the architecture/optimising compiler co-design space. [Citation Graph (, )][DBLP]

  6. Optimus: efficient realization of streaming applications on FPGAs. [Citation Graph (, )][DBLP]

  7. Compiling custom instructions onto expression-grained reconfigurable architectures. [Citation Graph (, )][DBLP]

  8. VESPA: portable, scalable, and flexible FPGA-based vector processors. [Citation Graph (, )][DBLP]

  9. Dynamic coprocessor management for FPGA-enhanced compute platforms. [Citation Graph (, )][DBLP]

  10. Power on demand for mobile computing devices. [Citation Graph (, )][DBLP]

  11. Efficiency and scalability of barrier synchronization on NoC based many-core architectures. [Citation Graph (, )][DBLP]

  12. Decoupled root scanning in multi-processor systems. [Citation Graph (, )][DBLP]

  13. SoC-C: efficient programming abstractions for heterogeneous multicore systems on chip. [Citation Graph (, )][DBLP]

  14. Reducing pressure in bounded DBT code caches. [Citation Graph (, )][DBLP]

  15. Efficient code caching to improve performance and energy consumption for java applications. [Citation Graph (, )][DBLP]

  16. Cache-aware cross-profiling for java processors. [Citation Graph (, )][DBLP]

  17. Predictable programming on a precision timed architecture. [Citation Graph (, )][DBLP]

  18. Advanced conservative and optimistic register coalescing. [Citation Graph (, )][DBLP]

  19. Control flow optimization in loops using interval analysis. [Citation Graph (, )][DBLP]

  20. Efficient vectorization of SIMD programs with non-aligned and irregular data access hardware. [Citation Graph (, )][DBLP]

  21. Comprehensive isomorphic subtree enumeration. [Citation Graph (, )][DBLP]

  22. Highly energy and performance efficient embedded computing through approximately correct arithmetic: a mathematical foundation and preliminary experimental validation. [Citation Graph (, )][DBLP]

  23. Multiple sleep mode leakage control for cache peripheral circuits in embedded processors. [Citation Graph (, )][DBLP]

  24. Design space exploration for field programmable compressor trees. [Citation Graph (, )][DBLP]

  25. Multi-granularity sampling for simulating concurrent heterogeneous applications. [Citation Graph (, )][DBLP]

  26. Active control and digital rights management of integrated circuit IP cores. [Citation Graph (, )][DBLP]

  27. A low-power parallel design of discrete wavelet transform using subthreshold voltage technology. [Citation Graph (, )][DBLP]

  28. Power management of MEMS-based storage devices for mobile systems. [Citation Graph (, )][DBLP]

  29. Execution context optimization for disk energy. [Citation Graph (, )][DBLP]

System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
System created by [] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002