The SCEAS System
Navigation Menu

Conferences in DBLP

International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES) (cases)
2009 (conf/cases/2009)

  1. Sustaining moore's law in embedded computing through probabilistic and approximate design: retrospects and prospects. [Citation Graph (, )][DBLP]

  2. Complete nanowire crossbar framework optimized for the multi-spacer patterning technique. [Citation Graph (, )][DBLP]

  3. III-V/Si integration: potential and outlook for integrated low power micro and nanosystems. [Citation Graph (, )][DBLP]

  4. Exploiting residue number system for power-efficient digital signal processing in embedded processors. [Citation Graph (, )][DBLP]

  5. Fast enumeration of maximal valid subgraphs for custom-instruction identification. [Citation Graph (, )][DBLP]

  6. Hybrid multithreading for VLIW processors. [Citation Graph (, )][DBLP]

  7. Spatial complexity of reversibly computable DAG. [Citation Graph (, )][DBLP]

  8. Mapping stream programs onto heterogeneous multiprocessor systems. [Citation Graph (, )][DBLP]

  9. Optimal loop parallelization for maximizing iteration-level parallelism. [Citation Graph (, )][DBLP]

  10. Progressive spill code placement. [Citation Graph (, )][DBLP]

  11. Slicing based code parallelization for minimizing inter-processor communication. [Citation Graph (, )][DBLP]

  12. Fine-grain performance scaling of soft vector processors. [Citation Graph (, )][DBLP]

  13. Fine-grained parallel application specific computing for RNA secondary structure prediction using SCFGS on FPGA. [Citation Graph (, )][DBLP]

  14. Reducing impact of cache miss stalls in embedded systems by extracting guaranteed independent instructions. [Citation Graph (, )][DBLP]

  15. Streaming FFT on REDEFINE-v2: an application-architecture design space exploration. [Citation Graph (, )][DBLP]

  16. A buffer replacement algorithm exploiting multi-chip parallelism in solid state disks. [Citation Graph (, )][DBLP]

  17. Exposing non-standard architectures to embedded software using compile-time virtualisation. [Citation Graph (, )][DBLP]

  18. A platform for developing adaptable multicore applications. [Citation Graph (, )][DBLP]

  19. Parallel, hardware-supported interrupt handling in an event-triggered real-time operating system. [Citation Graph (, )][DBLP]

  20. CheckerCore: enhancing an FPGA soft core to capture worst-case execution times. [Citation Graph (, )][DBLP]

  21. Instruction cache locking inside a binary rewriter. [Citation Graph (, )][DBLP]

  22. Tabu search-based synthesis of dynamically reconfigurable digital microfluidic biochips. [Citation Graph (, )][DBLP]

  23. Tight WCRT analysis of synchronous C programs. [Citation Graph (, )][DBLP]

  24. An accelerator-based wireless sensor network processor in 130nm CMOS. [Citation Graph (, )][DBLP]

  25. Smartphone-based assistive technologies for the blind. [Citation Graph (, )][DBLP]

  26. OPAIMS: open architecture precision agriculture information monitoring system. [Citation Graph (, )][DBLP]

  27. A case study of on-chip sensor network in multiprocessor system-on-chip. [Citation Graph (, )][DBLP]

  28. A fault tolerant cache architecture for sub 500mV operation: resizable data composer cache (RDC-cache). [Citation Graph (, )][DBLP]

  29. Towards scalable reliability frameworks for error prone CMPs. [Citation Graph (, )][DBLP]

  30. CGRA express: accelerating execution using dynamic operation fusion. [Citation Graph (, )][DBLP]

  31. Energy-aware probabilistic multiplier: design and analysis. [Citation Graph (, )][DBLP]

System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
System created by [] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002