Conferences in DBLP

International Conference on Computer Design (cdes)
2008 (conf/cdes/2008)

1. 
   R-tree: A Hardware Implementation. [Citation Graph (, )][DBLP]
   
   
2. 
   A Survey of Input Sensing and Processing Techniques for Multi-Touch Systems. [Citation Graph (, )][DBLP]
   
   
3. 
   CSPA: An Adder Faster Than Carry-Lookahead. [Citation Graph (, )][DBLP]
   
   
4. 
   Efficient Synthesis of Symmetric Function. [Citation Graph (, )][DBLP]
   
   
5. 
   Improved Implementation Choices for Iterative Improvement Partitioning Algorithms on Circuits. [Citation Graph (, )][DBLP]
   
   
6. 
   Finding Minimal ESCT Expressions for Boolean Functions with Weight of up to 7. [Citation Graph (, )][DBLP]
   
   
7. 
   Design of Low-area Rijndael Hardware Core. [Citation Graph (, )][DBLP]
   
   
8. 
   Transcoding Load Distribution Policy for Wireless Mobile Clients. [Citation Graph (, )][DBLP]
   
   
9. 
   Security of QImage File. [Citation Graph (, )][DBLP]
   
   
10. 
    Time-Domain Analysis of VLSI Interconnects Considering Oscillatory Inputs. [Citation Graph (, )][DBLP]
    
    
11. 
    Low Power Register File Design by Power Aware Register Assignment. [Citation Graph (, )][DBLP]
    
    
12. 
    The Effect of Number of Virtual Channels on NoC EDP. [Citation Graph (, )][DBLP]
    
    
13. 
    Limits of Dynamic Voltage and Frequency Scaling Algorithms. [Citation Graph (, )][DBLP]
    
    
14. 
    Effects of Register File Organization on Leakage Power Consumption. [Citation Graph (, )][DBLP]
    
    
15. 
    How to Really Save Computer Energy? [Citation Graph (, )][DBLP]
    
    
16. 
    A Specification Methodology for the Optimal Layout of a 2-Stage Interconnect Bus for Massively Parallel Architectures. [Citation Graph (, )][DBLP]
    
    
17. 
    A Quantum Algorithm for Finding Minimum Exclusive-Or Expressions for Multi-Output Incompletely Specified Boolean Functions. [Citation Graph (, )][DBLP]
    
    
18. 
    Scalable Directory Organization for Tiled CMP Architectures. [Citation Graph (, )][DBLP]
    
    
19. 
    A Novel Architecture for Fast Polynomial Division for Binary Coefficients. [Citation Graph (, )][DBLP]
    
    
20. 
    Embedding High-Performance Synchronous Routers to Asynchronous Network on Chip. [Citation Graph (, )][DBLP]
    
    
21. 
    Nanocompilation for the Cell Matrix Architecture. [Citation Graph (, )][DBLP]
    
    
22. 
    Single-Electron Tunneling Circuits for Image Processing Applications. [Citation Graph (, )][DBLP]
    
    
23. 
    Modeling Non-Iterated System Behavior with Chu Spaces. [Citation Graph (, )][DBLP]
    
    
24. 
    Low-Complexity Bypass Network Using Small RAM. [Citation Graph (, )][DBLP]
    
    
25. 
    A User-Space Device Driver Framework. [Citation Graph (, )][DBLP]
    
    
26. 
    A Multi-Block Interleaving Structure for NAND Flash Memory Storage. [Citation Graph (, )][DBLP]
    
    
27. 
    Capturing Dynamic Memory Structures. [Citation Graph (, )][DBLP]
    
    
28. 
    High Performance Cache. [Citation Graph (, )][DBLP]
    
    
29. 
    Image Reconstruction Using Reconfigurable Hardware. [Citation Graph (, )][DBLP]
    
    
30. 
    Analysis & Modeling of Substrate Noise in Domino CMOS Circuits. [Citation Graph (, )][DBLP]
    
    
31. 
    Subbus Control Line Impact on Effectiveness of Bus Encoding Schemes. [Citation Graph (, )][DBLP]
    
    
32. 
    A VHDL Design for PCA. [Citation Graph (, )][DBLP]
    
    
33. 
    Nanowire Crossbar PLA with Adaptive Variable Redundancy. [Citation Graph (, )][DBLP]
    
    
34. 
    High-Level Automatic Test Generation for VHDL Descriptions. [Citation Graph (, )][DBLP]
    
    
35. 
    An Approach for the Delay Simulation of D-Inverter in C-Ternary Logic Circuits. [Citation Graph (, )][DBLP]