Conferences in DBLP
A light-weight fairness mechanism for chip multiprocessor memory systems. [Citation Graph (, )][DBLP ] Extending concurrency of transactional memory programs by using value prediction. [Citation Graph (, )][DBLP ] Space-and-time efficient garbage collectors for parallel systems. [Citation Graph (, )][DBLP ] Core monitors: monitoring performance in multicore processors. [Citation Graph (, )][DBLP ] A study on optimally co-scheduling jobs of different lengths on chip multiprocessors. [Citation Graph (, )][DBLP ] A multi-streaming SIMD architecture for multimedia applications. [Citation Graph (, )][DBLP ] Quantitative analysis of sequence alignment applications on multiprocessor architectures. [Citation Graph (, )][DBLP ] Mapping the LU decomposition on a many-core architecture: challenges and solutions. [Citation Graph (, )][DBLP ] New applications of quantum algorithms to computer graphics: the quantum random sample consensus algorithm. [Citation Graph (, )][DBLP ] Towards automatic program partitioning. [Citation Graph (, )][DBLP ] Non-clairvoyant speed scaling for batched parallel jobs on multiprocessors. [Citation Graph (, )][DBLP ] Pleiad: a cross-environment middleware providing efficient multithreading on clusters. [Citation Graph (, )][DBLP ] Data parallel acceleration of decision support queries using Cell/BE and GPUs. [Citation Graph (, )][DBLP ] Wave field synthesis for 3D audio: architectural prospectives. [Citation Graph (, )][DBLP ] Accelerating total variation regularization for matrix-valued images on GPUs. [Citation Graph (, )][DBLP ] A control-structure splitting optimization for GPGPU. [Citation Graph (, )][DBLP ] Improving performance of simple cores by exploiting loop-level parallelism through value prediction and reconfiguration. [Citation Graph (, )][DBLP ] Scheduling dynamic parallelism on accelerators. [Citation Graph (, )][DBLP ] Power consumption and reduction in a real, commercial multimedia core. [Citation Graph (, )][DBLP ] High-performance SIMT code generation in an active visual effects library. [Citation Graph (, )][DBLP ] True value: assessing and optimizing the cost of computing at the data center level. [Citation Graph (, )][DBLP ] High accuracy failure injection in parallel and distributed systems using virtualization. [Citation Graph (, )][DBLP ] Scalable transparent checkpoint-restart of global address space applications on virtual machines over infiniband. [Citation Graph (, )][DBLP ] Evaluating multi-core platforms for HPC data-intensive kernels. [Citation Graph (, )][DBLP ] Strategies for dynamic memory allocation in hybrid architectures. [Citation Graph (, )][DBLP ] Characterizing the performance penalties induced by irregular code using pointer structures and indirection arrays on the intel core 2 architecture. [Citation Graph (, )][DBLP ] Larrabee: a many-core Intel architecture for visual computing. [Citation Graph (, )][DBLP ] Pervasive massively multithreaded GPU processors. [Citation Graph (, )][DBLP ] 