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Conferences in DBLP

International Conference on Hardware Software Codesign (codes)
2007 (conf/codes/2007)

  1. Beyond gaming: programming the PLAYSTATION®3 cell architecture for cost-effective parallel processing. [Citation Graph (, )][DBLP]

  2. Compiling code accelerators for FPGAs. [Citation Graph (, )][DBLP]

  3. Simultaneous synthesis of buses, data mapping and memory allocation for MPSoC. [Citation Graph (, )][DBLP]

  4. A framework for rapid system-level exploration, synthesis, and programming of multimedia MP-SoCs. [Citation Graph (, )][DBLP]

  5. Predictable execution adaptivity through embedding dynamic reconfigurability into static MPSoC schedules. [Citation Graph (, )][DBLP]

  6. Synchronization after design refinements with sensitive delay elements. [Citation Graph (, )][DBLP]

  7. Embedded software development on top of transaction-level models. [Citation Graph (, )][DBLP]

  8. Pointer re-coding for creating definitive MPSoC models. [Citation Graph (, )][DBLP]

  9. Dynamic security domain scaling on symmetric multiprocessors for future high-end embedded systems. [Citation Graph (, )][DBLP]

  10. Secure FPGA circuits using controlled placement and routing. [Citation Graph (, )][DBLP]

  11. A smart random code injection to mask power analysis based side channel attacks. [Citation Graph (, )][DBLP]

  12. Ensuring secure program execution in multiprocessor embedded systems: a case study. [Citation Graph (, )][DBLP]

  13. Combined approach to system level performance analysis of embedded systems. [Citation Graph (, )][DBLP]

  14. Event-based re-training of statistical contention models for heterogeneous multiprocessors. [Citation Graph (, )][DBLP]

  15. HySim: a fast simulation framework for embedded software development. [Citation Graph (, )][DBLP]

  16. A computational reflection mechanism to support platform debugging in SystemC. [Citation Graph (, )][DBLP]

  17. Energy efficient co-scheduling in dynamically reconfigurable systems. [Citation Graph (, )][DBLP]

  18. Thread warping: a framework for dynamic synthesis of thread accelerators. [Citation Graph (, )][DBLP]

  19. HW/SW co-design for Esterel processing. [Citation Graph (, )][DBLP]

  20. Power deregulation: eliminating off-chip voltage regulation circuitry from embedded systems. [Citation Graph (, )][DBLP]

  21. Temperature-aware processor frequency assignment for MPSoCs using convex optimization. [Citation Graph (, )][DBLP]

  22. Three-dimensional multiprocessor system-on-chip thermal optimization. [Citation Graph (, )][DBLP]

  23. Complexity challenges towards 4th generation communication solutions. [Citation Graph (, )][DBLP]

  24. Fresh air: the emerging landscape of design for networked embedded systems. [Citation Graph (, )][DBLP]

  25. Locality optimization in wireless applications. [Citation Graph (, )][DBLP]

  26. A code-generator generator for multi-output instructions. [Citation Graph (, )][DBLP]

  27. Influence of procedure cloning on WCET prediction. [Citation Graph (, )][DBLP]

  28. Compile-time decided instruction cache locking using worst-case execution paths. [Citation Graph (, )][DBLP]

  29. Channel trees: reducing latency by sharing time slots in time-multiplexed networks on chip. [Citation Graph (, )][DBLP]

  30. Performance and resource optimization of NoC router architecture for master and slave IP cores. [Citation Graph (, )][DBLP]

  31. Incremental run-time application mapping for homogeneous NoCs with multiple voltage levels. [Citation Graph (, )][DBLP]

  32. A data protection unit for NoC-based architectures. [Citation Graph (, )][DBLP]

  33. Complex task activation schemes in system level performance analysis. [Citation Graph (, )][DBLP]

  34. Improved response time analysis of tasks scheduled under preemptive Round-Robin. [Citation Graph (, )][DBLP]

  35. Probabilistic performance risk analysis at system-level. [Citation Graph (, )][DBLP]

  36. ESL design and HW/SW co-verification of high-end software defined radio platforms. [Citation Graph (, )][DBLP]

  37. Smart driver for power reduction in next generation bistable electrophoretic display technology. [Citation Graph (, )][DBLP]

  38. On the impact of manufacturing process variations on the lifetime of sensor networks. [Citation Graph (, )][DBLP]

  39. Performance modeling for early analysis of multi-core systems. [Citation Graph (, )][DBLP]

  40. Bridging gap between simulation and spreadsheet study. [Citation Graph (, )][DBLP]

  41. Performance analysis and design space exploration for high-end biomedical applications: challenges and solutions. [Citation Graph (, )][DBLP]

  42. A low power VLIW processor generation method by means of extracting non-redundant activation conditions. [Citation Graph (, )][DBLP]

  43. Scheduling and voltage scaling for energy/reliability trade-offs in fault-tolerant time-triggered embedded systems. [Citation Graph (, )][DBLP]

  44. Reliable multiprocessor system-on-chip synthesis. [Citation Graph (, )][DBLP]

  45. Aggressive snoop reduction for synchronized producer-consumer communication in energy-efficient embedded multi-processors. [Citation Graph (, )][DBLP]

  46. Predator: a predictable SDRAM memory controller. [Citation Graph (, )][DBLP]

  47. Performance improvement of block based NAND flash translation layer. [Citation Graph (, )][DBLP]

  48. Automotive networks: are new busses and gateways the answer or just another challenge? [Citation Graph (, )][DBLP]

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The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
System created by [] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002