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Conferences in DBLP

International Conference on Hardware Software Codesign (codes)
2008 (conf/codes/2008)

  1. Synthesis of heterogeneous pipelined multiprocessor systems using ILP: jpeg case study. [Citation Graph (, )][DBLP]

  2. Concurrency emulation and analysis of parallel applications for multi-processor system-on-chip co-design. [Citation Graph (, )][DBLP]

  3. A time-predictable system initialization design for huge-capacity flash-memory storage systems. [Citation Graph (, )][DBLP]

  4. Deterministic service guarantees for nand flash using partial block cleaning. [Citation Graph (, )][DBLP]

  5. Static analysis of processor stall cycle aggregation. [Citation Graph (, )][DBLP]

  6. Application specific non-volatile primary memory for embedded systems. [Citation Graph (, )][DBLP]

  7. Scratchpad allocation for concurrent embedded software. [Citation Graph (, )][DBLP]

  8. Software optimization for MPSoC: a mpeg-2 decoder case study. [Citation Graph (, )][DBLP]

  9. Hardware/software partitioning of floating point software applications to fixed-pointed coprocessor circuits. [Citation Graph (, )][DBLP]

  10. A performance-oriented hardware/software partitioning for datapath applications. [Citation Graph (, )][DBLP]

  11. Traversal caches: a first step towards FPGA acceleration of pointer-based data structures. [Citation Graph (, )][DBLP]

  12. Specification and OS-based implementation of self-adaptive, hardware/software embedded systems. [Citation Graph (, )][DBLP]

  13. Distributed and low-power synchronization architecture for embedded multiprocessors. [Citation Graph (, )][DBLP]

  14. LOCS: a low overhead profiler-driven design flow for security of MPSoCs. [Citation Graph (, )][DBLP]

  15. Online adaptive utilization control for real-time embedded multiprocessor systems. [Citation Graph (, )][DBLP]

  16. Intra- and inter-processor hybrid performance modeling for MPSoC architectures. [Citation Graph (, )][DBLP]

  17. Dynamic tuning of configurable architectures: the AWW online algorithm. [Citation Graph (, )][DBLP]

  18. Static analysis for fast and accurate design space exploration of caches. [Citation Graph (, )][DBLP]

  19. Profiling of lossless-compression algorithms for a novel biomedical-implant architecture. [Citation Graph (, )][DBLP]

  20. Holistic design and caching in mobile computing. [Citation Graph (, )][DBLP]

  21. You can catch more bugs with transaction level honey. [Citation Graph (, )][DBLP]

  22. Simulation and embedded software development for Anton, a parallel machine with heterogeneous multicore ASICs. [Citation Graph (, )][DBLP]

  23. Model checking SystemC designs using timed automata. [Citation Graph (, )][DBLP]

  24. Specification-based compaction of directed tests for functional validation of pipelined processors. [Citation Graph (, )][DBLP]

  25. Combination of instruction set simulation and abstract RTOS model execution for fast and accurate target software evaluation. [Citation Graph (, )][DBLP]

  26. Cache-aware optimization of BAN applications. [Citation Graph (, )][DBLP]

  27. Don't forget memories: a case study redesigning a pattern counting ASIC circuit for FPGAs. [Citation Graph (, )][DBLP]

  28. Reliable performance analysis of a multicore multithreaded system-on-chip. [Citation Graph (, )][DBLP]

  29. Extending open core protocol to support system-level cache coherence. [Citation Graph (, )][DBLP]

  30. Performance debugging of Esterel specifications. [Citation Graph (, )][DBLP]

  31. SPaC: a symbolic pareto calculator. [Citation Graph (, )][DBLP]

  32. Providing accurate event models for the analysis of heterogeneous multiprocessor systems. [Citation Graph (, )][DBLP]

  33. Highly-cited ideas in system codesign and synthesis. [Citation Graph (, )][DBLP]

  34. A security monitoring service for NoCs. [Citation Graph (, )][DBLP]

  35. ODOR: a microresonator-based high-performance low-cost router for optical networks-on-Chip. [Citation Graph (, )][DBLP]

  36. Asynchronous transient resilient links for NoC. [Citation Graph (, )][DBLP]

  37. Distributed flit-buffer flow control for networks-on-chip. [Citation Graph (, )][DBLP]

  38. Co-design in the wilderness. [Citation Graph (, )][DBLP]

  39. Design and defect tolerance beyond CMOS. [Citation Graph (, )][DBLP]

  40. Slack analysis in the system design loop. [Citation Graph (, )][DBLP]

  41. Symbolic voter placement for dependability-aware system synthesis. [Citation Graph (, )][DBLP]

  42. Speculative DMA for architecturally visible storage in instruction set extensions. [Citation Graph (, )][DBLP]

  43. Yield maximization for system-level task assignment and configuration selection of configurable multiprocessors. [Citation Graph (, )][DBLP]

  44. Methodology for multi-granularity embedded processor power model generation for an ESL design flow. [Citation Graph (, )][DBLP]

  45. Power reduction via macroblock prioritization for power aware H.264 video applications. [Citation Graph (, )][DBLP]

  46. Guaranteed scheduling for repetitive hard real-time tasks under the maximal temperature constraint. [Citation Graph (, )][DBLP]

  47. System-level mitigation of WID leakage power variability using body-bias islands. [Citation Graph (, )][DBLP]

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The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
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for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002