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Conferences in DBLP

International Conference on Hardware Software Codesign (codes)
2009 (conf/codes/2009)

  1. A compositional modelling framework for exploring MPSoC systems. [Citation Graph (, )][DBLP]

  2. A high-level virtual platform for early MPSoC software development. [Citation Graph (, )][DBLP]

  3. Portable SystemC-on-a-chip. [Citation Graph (, )][DBLP]

  4. On compile-time evaluation of process partitioning transformations for Kahn process networks. [Citation Graph (, )][DBLP]

  5. SARA: StreAm register allocation. [Citation Graph (, )][DBLP]

  6. Dynamically utilizing computation accelerators for extensible processors in a software approach. [Citation Graph (, )][DBLP]

  7. An efficient technique for analysis of minimal buffer requirements of synchronous dataflow graphs with model checking. [Citation Graph (, )][DBLP]

  8. Using binary translation in event driven simulation for fast and flexible MPSoC simulation. [Citation Graph (, )][DBLP]

  9. Configuration and control of SystemC models using TLM middleware. [Citation Graph (, )][DBLP]

  10. Scalable and retargetable simulation techniquesfor multiprocessor systems. [Citation Graph (, )][DBLP]

  11. An on-chip interconnect and protocol stack for multiple communication paradigms and programming models. [Citation Graph (, )][DBLP]

  12. A monitoring and adaptive routing mechanism for QoS traffic on mesh NoC architectures. [Citation Graph (, )][DBLP]

  13. A DP-network for optimal dynamic routing in network-on-chip. [Citation Graph (, )][DBLP]

  14. Exploring hybrid photonic networks-on-chip foremerging chip multiprocessors. [Citation Graph (, )][DBLP]

  15. LOP: a novel SRAM-based architecture for low power and high throughput packet classification. [Citation Graph (, )][DBLP]

  16. Memory-efficient distribution of regular expressions for fast deep packet inspection. [Citation Graph (, )][DBLP]

  17. On-the-fly hardware acceleration for protocol stack processing in next generation mobile devices. [Citation Graph (, )][DBLP]

  18. FRA: a flash-aware redundancy array of flash storage devices. [Citation Graph (, )][DBLP]

  19. Automatic customization of device drivers for IP-cores used with assorted CPU organizations. [Citation Graph (, )][DBLP]

  20. An MDP-based application oriented optimal policy for wireless sensor networks. [Citation Graph (, )][DBLP]

  21. A standby-sparing technique with low energy-overhead for fault-tolerant hard real-time systems. [Citation Graph (, )][DBLP]

  22. Efficient dynamic voltage/frequency scaling through algorithmic loop transformation. [Citation Graph (, )][DBLP]

  23. Energy-efficiency for multiframe real-time tasks on a dynamic voltage scaling processor. [Citation Graph (, )][DBLP]

  24. A variation-tolerant scheduler for better than worst-case behavioral synthesis. [Citation Graph (, )][DBLP]

  25. Exploiting data-redundancy in reliability-aware networked embedded system design. [Citation Graph (, )][DBLP]

  26. ESL power analysis of embedded processors for temperature and reliability estimations. [Citation Graph (, )][DBLP]

  27. Squashing microcode stores to size in embedded systems while delivering rapid microcode accesses. [Citation Graph (, )][DBLP]

  28. Stack oriented data cache filtering. [Citation Graph (, )][DBLP]

  29. ILP optimal scheduling for multi-module memory. [Citation Graph (, )][DBLP]

  30. Cycle count accurate memory modeling in system level design. [Citation Graph (, )][DBLP]

  31. SuSeSim: a fast simulation strategy to find optimal L1 cache configuration for embedded systems. [Citation Graph (, )][DBLP]

  32. TotalProf: a fast and accurate retargetable source code profiler. [Citation Graph (, )][DBLP]

  33. Using continuous statistical machine learning to enable high-speed performance prediction in hybrid instruction-/cycle-accurate instruction set simulators. [Citation Graph (, )][DBLP]

  34. Minimization of the reconfiguration latency for the mapping of applications on FPGA-based systems. [Citation Graph (, )][DBLP]

  35. MinDeg: a performance-guided replacement policy for run-time reconfigurable accelerators. [Citation Graph (, )][DBLP]

  36. Supporting RTL flow compatibility in a microarchitecture-level design framework. [Citation Graph (, )][DBLP]

  37. A scalable parallel H.264 decoder on the cell broadband engine architecture. [Citation Graph (, )][DBLP]

  38. FlexRay schedule optimization of the static segment. [Citation Graph (, )][DBLP]

  39. Improving application launch times with hybrid disks. [Citation Graph (, )][DBLP]

  40. A tuneable software cache coherence protocol for heterogeneous MPSoCs. [Citation Graph (, )][DBLP]

  41. Building heterogeneous reconfigurable systems with a hardware microkernel. [Citation Graph (, )][DBLP]

  42. Native MPSoC co-simulation environment for software performance estimation. [Citation Graph (, )][DBLP]

  43. Fast model-based test case classification for performance analysis of multimedia MPSoC platforms. [Citation Graph (, )][DBLP]

  44. Bottom-up performance analysis considering time slice based software scheduling at system level. [Citation Graph (, )][DBLP]

  45. A recursive approach to end-to-end path latency computation in heterogeneous multiprocessor systems. [Citation Graph (, )][DBLP]

  46. Mapping pipelined applications onto heterogeneous embedded systems: a bayesian optimization algorithm based approach. [Citation Graph (, )][DBLP]

  47. Applying network calculus for performance analysis of self-similar traffic in on-chip networks. [Citation Graph (, )][DBLP]

  48. Statistical physics approaches for network-on-chip traffic characterization. [Citation Graph (, )][DBLP]

  49. Automated technique for design of NoC with minimal communication latency. [Citation Graph (, )][DBLP]

  50. Synthesis of topology configurations and deadlock free routing algorithms for ReNoC-based systems-on-chip. [Citation Graph (, )][DBLP]

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The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
System created by [] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002