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Conferences in DBLP

Design Automation Conference (DAC) (dac)
2008 (conf/dac/2008)

  1. Flow engineering for physical implementation: theory and practice. [Citation Graph (, )][DBLP]

  2. Sparse matrix computations on manycore GPU's. [Citation Graph (, )][DBLP]

  3. Parallel programming: can we PLEASE get it right this time? [Citation Graph (, )][DBLP]

  4. Parallelizing CAD: a timely research agenda for EDA. [Citation Graph (, )][DBLP]

  5. Functionally linear decomposition and synthesis of logic circuits for FPGAs. [Citation Graph (, )][DBLP]

  6. FPGA area reduction by multi-output function based sequential resynthesis. [Citation Graph (, )][DBLP]

  7. A generalized network flow based algorithm for power-aware FPGA memory mapping. [Citation Graph (, )][DBLP]

  8. Enhancing timing-driven FPGA placement for pipelined netlists. [Citation Graph (, )][DBLP]

  9. Statistical regression for efficient high-dimensional modeling of analog and mixed-signal performance variations. [Citation Graph (, )][DBLP]

  10. Topology synthesis of analog circuits based on adaptively generated building blocks. [Citation Graph (, )][DBLP]

  11. Analog placement based on hierarchical module clustering. [Citation Graph (, )][DBLP]

  12. Run-time instruction set selection in a transmutable embedded processor. [Citation Graph (, )][DBLP]

  13. Rapid application specific floating-point unit generation with bit-alignment. [Citation Graph (, )][DBLP]

  14. Dynamic register file resizing and frequency scaling to improve embedded processor performance and energy-delay efficiency. [Citation Graph (, )][DBLP]

  15. C-based design flow: a case study on G.729A for voice over internet protocol (VoIP). [Citation Graph (, )][DBLP]

  16. Election year: what the electronics industry needs---and can expect---from the incoming administration. [Citation Graph (, )][DBLP]

  17. A 242mW, 10mm21080p H.264/AVC high profile encoder chip. [Citation Graph (, )][DBLP]

  18. The design of a low power carbon nanotube chemical sensor system. [Citation Graph (, )][DBLP]

  19. iVisual: an intelligent visual sensor SoC with 2790fps CMOS image sensor and 205GOPS/W vision processor. [Citation Graph (, )][DBLP]

  20. Vision platform for mobile intelligent robot based on 81.6 GOPS object recognition processor. [Citation Graph (, )][DBLP]

  21. A MIPS R2000 implementation. [Citation Graph (, )][DBLP]

  22. Process variation tolerant SRAM array for ultra low voltage applications. [Citation Graph (, )][DBLP]

  23. PicoCube: a 1 cm3 sensor node powered by harvested energy. [Citation Graph (, )][DBLP]

  24. An 8x8 run-time reconfigurable FPGA embedded in a SoC. [Citation Graph (, )][DBLP]

  25. Reinventing EDA with manycore processors. [Citation Graph (, )][DBLP]

  26. Multicore design is the challenge! what is the solution? [Citation Graph (, )][DBLP]

  27. Compositional verification of retiming and sequential optimizations. [Citation Graph (, )][DBLP]

  28. Tunneling and slicing: towards scalable BMC. [Citation Graph (, )][DBLP]

  29. Optimizing automatic abstraction refinement for generalized symbolic trajectory evaluation. [Citation Graph (, )][DBLP]

  30. Faster symmetry discovery using sparsity of symmetries. [Citation Graph (, )][DBLP]

  31. Application-driven floorplan-aware voltage island design. [Citation Graph (, )][DBLP]

  32. DeFer: deferred decision making enabled fixed-outline floorplanner. [Citation Graph (, )][DBLP]

  33. Routability-driven analytical placement by net overlapping removal for large-scale mixed-size designs. [Citation Graph (, )][DBLP]

  34. Broadcast electrode-addressing for pin-constrained multi-functional digital microfluidic biochips. [Citation Graph (, )][DBLP]

  35. Optimality and improvement of dynamic voltage scaling algorithms for multimedia applications. [Citation Graph (, )][DBLP]

  36. Feedback-controlled reliability-aware power management for real-time embedded systems. [Citation Graph (, )][DBLP]

  37. Energy-optimal software partitioning in heterogeneous multiprocessor embedded systems. [Citation Graph (, )][DBLP]

  38. Customizing computation accelerators for extensible multi-issue processors with effective optimization techniques. [Citation Graph (, )][DBLP]

  39. An automatic scratch pad memory management tool and MPEG-4 encoder case study. [Citation Graph (, )][DBLP]

  40. A methodology for statistical estimation of read access yield in SRAMs. [Citation Graph (, )][DBLP]

  41. Automated design of self-adjusting pipelines. [Citation Graph (, )][DBLP]

  42. Speedpath prediction based on learning from a small set of examples. [Citation Graph (, )][DBLP]

  43. Timing yield driven clock skew scheduling considering non-Gaussian distributions of critical path delays. [Citation Graph (, )][DBLP]

  44. Statistical waveform and current source based standard cell models for accurate timing analysis. [Citation Graph (, )][DBLP]

  45. SystemVerilog implicit port enhancements accelerate system design & verification. [Citation Graph (, )][DBLP]

  46. Translation of an existing VMM-based SystemVerilog testbench to OVM. [Citation Graph (, )][DBLP]

  47. WavePipe: parallel transient simulation of analog and digital circuits on multi-core shared-memory machines. [Citation Graph (, )][DBLP]

  48. The mixed signal optimum energy point: voltage and parallelism. [Citation Graph (, )][DBLP]

  49. Analysis and implications of parasitic and screening effects on the high-frequency/RF performance of tunneling-carbon nanotube FETs. [Citation Graph (, )][DBLP]

  50. Assertion-based verification of a 32 thread SPARCTM CMT microprocessor. [Citation Graph (, )][DBLP]

  51. Functional test selection based on unsupervised support vector analysis. [Citation Graph (, )][DBLP]

  52. Early formal verification of conditional coverage points to identify intrinsically hard-to-verify logic. [Citation Graph (, )][DBLP]

  53. Technology exploration for graphene nanoribbon FETs. [Citation Graph (, )][DBLP]

  54. Modeling of failure probability and statistical design of spin-torque transfer magnetic random access memory (STT MRAM) array for yield enhancement. [Citation Graph (, )][DBLP]

  55. A progressive-ILP based routing algorithm for cross-referencing biochips. [Citation Graph (, )][DBLP]

  56. High-performance timing simulation of embedded software. [Citation Graph (, )][DBLP]

  57. Model checking based analysis of end-to-end latency in embedded, real-time systems with clock drifts. [Citation Graph (, )][DBLP]

  58. Exploring locking & partitioning for predictable shared caches on multi-cores. [Citation Graph (, )][DBLP]

  59. Miss reduction in embedded processors through dynamic, power-friendly cache design. [Citation Graph (, )][DBLP]

  60. ESL hand-off: fact or EDA fiction? [Citation Graph (, )][DBLP]

  61. Characterizing chip-multiprocessor variability-tolerance. [Citation Graph (, )][DBLP]

  62. Cache modeling in probabilistic execution time analysis. [Citation Graph (, )][DBLP]

  63. Multiprocessor performance estimation using hybrid simulation. [Citation Graph (, )][DBLP]

  64. Multithreaded simulation for synchronous dataflow graphs. [Citation Graph (, )][DBLP]

  65. Design of a mask-programmable memory/multiplier array using G4-FET technology. [Citation Graph (, )][DBLP]

  66. Programmable logic circuits based on ambipolar CNFET. [Citation Graph (, )][DBLP]

  67. Analog parallelism in ring-based VCOs. [Citation Graph (, )][DBLP]

  68. Techniques for fully integrated intra-/inter-chip optical communication. [Citation Graph (, )][DBLP]

  69. How to let instruction set processor beat ASIC for low power wireless baseband implementation: a system level approach. [Citation Graph (, )][DBLP]

  70. Bounded-lifetime integrated circuits. [Citation Graph (, )][DBLP]

  71. Collective computing based on swarm intelligence. [Citation Graph (, )][DBLP]

  72. (Bio)-behavioral CAD. [Citation Graph (, )][DBLP]

  73. Next generation wireless-multimedia devices: who is up for the challenge? [Citation Graph (, )][DBLP]

  74. Statistical diagnosis of unmodeled systematic timing effects. [Citation Graph (, )][DBLP]

  75. Multiple defect diagnosis using no assumptions on failing pattern characteristics. [Citation Graph (, )][DBLP]

  76. Precise failure localization using automated layout analysis of diagnosis candidates. [Citation Graph (, )][DBLP]

  77. IFRA: instruction footprint recording and analysis for post-silicon bug localization in processors. [Citation Graph (, )][DBLP]

  78. Automatic architecture refinement techniques for customizing processing elements. [Citation Graph (, )][DBLP]

  79. Formal datapath representation and manipulation for implementing DSP transforms. [Citation Graph (, )][DBLP]

  80. Symbolic noise analysis approach to computational hardware optimization. [Citation Graph (, )][DBLP]

  81. Optimizing imprecise fixed-point arithmetic circuits specified by Taylor Series through arithmetic transform. [Citation Graph (, )][DBLP]

  82. Parameterized timing analysis with general delay models and arbitrary variation sources. [Citation Graph (, )][DBLP]

  83. DeMOR: decentralized model order reduction of linear networks with massive ports. [Citation Graph (, )][DBLP]

  84. Stochastic integral equation solver for efficient variation-aware interconnect extraction. [Citation Graph (, )][DBLP]

  85. Electric field integral equation combined with cylindrical conduction mode basis functions for electrical modeling of three-dimensional interconnects. [Citation Graph (, )][DBLP]

  86. Driver waveform computation for timing analysis with multiple voltage threshold driver models. [Citation Graph (, )][DBLP]

  87. Binary de Bruijn on-chip network for a flexible multiprocessor LDPC decoder. [Citation Graph (, )][DBLP]

  88. An area-efficient high-throughput hybrid interconnection network for single-chip parallel processing. [Citation Graph (, )][DBLP]

  89. A reconfigurable routing algorithm for a fault-tolerant 2D-Mesh Network-on-Chip. [Citation Graph (, )][DBLP]

  90. A practical approach of memory access parallelization to exploit multiple off-chip DDR memories. [Citation Graph (, )][DBLP]

  91. Towards a more physical approach to gate modeling for timing, noise, and power. [Citation Graph (, )][DBLP]

  92. Transistor level gate modeling for accurate and fast timing, noise, and power analysis. [Citation Graph (, )][DBLP]

  93. A "true" electrical cell model for timing, noise, and power grid verification. [Citation Graph (, )][DBLP]

  94. Challenges in gate level modeling for delay and SI at 65nm and below. [Citation Graph (, )][DBLP]

  95. Addressing library creation challenges from recent Liberty extensions. [Citation Graph (, )][DBLP]

  96. SystemClick: a domain-specific framework for early exploration using functional performance models. [Citation Graph (, )][DBLP]

  97. Applying passive RFID system to wireless headphones for extreme low power consumption. [Citation Graph (, )][DBLP]

  98. Pro-VIZOR: process tunable virtually zero margin low power adaptive RF for wireless systems. [Citation Graph (, )][DBLP]

  99. Automated design of tunable impedance matching networks for reconfigurable wireless applications. [Citation Graph (, )][DBLP]

  100. ELIAD: efficient lithography aware detailed router with compact post-OPC printability prediction. [Citation Graph (, )][DBLP]

  101. Predictive formulae for OPC with applications to lithography-friendly routing. [Citation Graph (, )][DBLP]

  102. Dose map and placement co-optimization for timing yield enhancement and leakage power reduction. [Citation Graph (, )][DBLP]

  103. Design-process integration for performance-based OPC framework. [Citation Graph (, )][DBLP]

  104. An efficient incremental algorithm for min-area retiming. [Citation Graph (, )][DBLP]

  105. Scalable min-register retiming under timing and initializability constraints. [Citation Graph (, )][DBLP]

  106. Merging nodes under sequential observability. [Citation Graph (, )][DBLP]

  107. N-variant IC design: methodology and applications. [Citation Graph (, )][DBLP]

  108. Verifying really complex systems: on earth and beyond. [Citation Graph (, )][DBLP]

  109. Circuit and microarchitecture evaluation of 3D stacking magnetic RAM (MRAM) as a universal memory replacement. [Citation Graph (, )][DBLP]

  110. Automatic package and board decoupling capacitor placement using genetic algorithms and M-FDM. [Citation Graph (, )][DBLP]

  111. Topological routing to maximize routability for package substrate. [Citation Graph (, )][DBLP]

  112. Low power passive equalizer optimization using tritonic step response. [Citation Graph (, )][DBLP]

  113. Daedalus: toward composable multimedia MP-SoC design. [Citation Graph (, )][DBLP]

  114. SystemCoDesigner: automatic design space exploration and rapid prototyping from behavioral models. [Citation Graph (, )][DBLP]

  115. Specify-explore-refine (SER): from specification to implementation. [Citation Graph (, )][DBLP]

  116. Standard interfaces in mobile terminals: increasing the efficiency of device design and accelerating innovation. [Citation Graph (, )][DBLP]

  117. Holistic pathfinding: virtual wireless chip design for advanced technology and design exploration. [Citation Graph (, )][DBLP]

  118. Full-chip leakage analysis in nano-scale technologies: mechanisms, variation sources, and verification. [Citation Graph (, )][DBLP]

  119. Multiobjective optimization of sleep vector for zigzag power-gated circuits in standard cell elements. [Citation Graph (, )][DBLP]

  120. Input vector control for post-silicon leakage current minimization in the presence of manufacturing variability. [Citation Graph (, )][DBLP]

  121. Leakage power-aware clock skew scheduling: converting stolen time into leakage power reduction. [Citation Graph (, )][DBLP]

  122. Variation-adaptive feedback control for networks-on-chip with multiple clock domains. [Citation Graph (, )][DBLP]

  123. Application mapping for chip multiprocessors. [Citation Graph (, )][DBLP]

  124. Concurrent topology and routing optimization in automotive network integration. [Citation Graph (, )][DBLP]

  125. A dynamically-allocated virtual channel architecture with congestion awareness for on-chip routers. [Citation Graph (, )][DBLP]

  126. Keeping hot chips cool: are IC thermal problems hot air? [Citation Graph (, )][DBLP]

  127. Bi-decomposing large Boolean functions via interpolation and satisfiability solving. [Citation Graph (, )][DBLP]

  128. Signature based Boolean matching in the presence of don't cares. [Citation Graph (, )][DBLP]

  129. The synthesis of robust polynomial arithmetic with stochastic logic. [Citation Graph (, )][DBLP]

  130. Automatic synthesis of clock gating logic with controlled netlist perturbation. [Citation Graph (, )][DBLP]

  131. A new paradigm for synthesis and propagation of clock gating conditions. [Citation Graph (, )][DBLP]

  132. 3-D semiconductor's: more from Moore. [Citation Graph (, )][DBLP]

  133. Tera-scale computing and interconnect challenges. [Citation Graph (, )][DBLP]

  134. Design and CAD for 3D integrated circuits. [Citation Graph (, )][DBLP]

  135. Why should we do 3D integration? [Citation Graph (, )][DBLP]

  136. Efficient Monte Carlo based incremental statistical timing analysis. [Citation Graph (, )][DBLP]

  137. Generalized Krylov recycling methods for solution of multiple related linear equation systems in electromagnetic analysis. [Citation Graph (, )][DBLP]

  138. A framework for block-based timing sensitivity analysis. [Citation Graph (, )][DBLP]

  139. Accurate and analytical statistical spatial correlation modeling for VLSI DFM applications. [Citation Graph (, )][DBLP]

  140. Non-parametric statistical static timing analysis: an SSTA framework for arbitrary distribution. [Citation Graph (, )][DBLP]

  141. An integrated nonlinear placement framework with congestion and porosity aware buffer planning. [Citation Graph (, )][DBLP]

  142. Circuit-wise buffer insertion and gate sizing algorithm with scalability. [Citation Graph (, )][DBLP]

  143. Type-matching clock tree for zero skew clock gating. [Citation Graph (, )][DBLP]

  144. Robust chip-level clock tree synthesis for SOC designs. [Citation Graph (, )][DBLP]

  145. Path smoothing via discrete optimization. [Citation Graph (, )][DBLP]

  146. Stochastic modeling of a thermally-managed multi-core system. [Citation Graph (, )][DBLP]

  147. Predictive dynamic thermal management for multicore systems. [Citation Graph (, )][DBLP]

  148. Control theory-based DVS for interactive 3D games. [Citation Graph (, )][DBLP]

  149. Many-core design from a thermal perspective. [Citation Graph (, )][DBLP]

  150. Compiler-driven register re-assignment for register file power-density and temperature reduction. [Citation Graph (, )][DBLP]

  151. MAPS: an integrated framework for MPSoC application parallelization. [Citation Graph (, )][DBLP]

  152. ADAM: run-time agent-based distributed application mapping for on-chip communication. [Citation Graph (, )][DBLP]

  153. Latency and bandwidth efficient communication through system customization for embedded multiprocessors. [Citation Graph (, )][DBLP]

  154. Federation: repurposing scalar cores for out-of-order instruction issue. [Citation Graph (, )][DBLP]

  155. ETAHM: an energy-aware task allocation algorithm for heterogeneous multiprocessor. [Citation Graph (, )][DBLP]

  156. A practical reconfigurable hardware accelerator for Boolean satisfiability solvers. [Citation Graph (, )][DBLP]

  157. Reconfigurable computing using content addressable memory for improved performance and resource usage. [Citation Graph (, )][DBLP]

  158. Automated transistor sizing for FPGA architecture exploration. [Citation Graph (, )][DBLP]

  159. TuneFPGA: post-silicon tuning of dual-Vdd FPGAs. [Citation Graph (, )][DBLP]

  160. Strategies for mainstream usage of formal verification. [Citation Graph (, )][DBLP]

  161. Pre-RTL formal verification: an intel experience. [Citation Graph (, )][DBLP]

  162. Challenges in using system-level models for RTL verification. [Citation Graph (, )][DBLP]

  163. Leveraging sequential equivalence checking to enable system-level to RTL flows. [Citation Graph (, )][DBLP]

  164. Towards acceleration of fault simulation using graphics processing units. [Citation Graph (, )][DBLP]

  165. Scan chain clustering for test power reduction. [Citation Graph (, )][DBLP]

  166. On reliable modular testing with vulnerable test access mechanisms. [Citation Graph (, )][DBLP]

  167. On tests to detect via opens in digital CMOS circuits. [Citation Graph (, )][DBLP]

  168. Protecting bus-based hardware IP by secret sharing. [Citation Graph (, )][DBLP]

  169. Design of high performance pattern matching engine through compact deterministic finite automata. [Citation Graph (, )][DBLP]

  170. SHIELD: a software hardware design methodology for security and reliability of MPSoCs. [Citation Graph (, )][DBLP]

  171. A multi-resolution AHB bus tracer for real-time compression of forward/backward traces in a circular buffer. [Citation Graph (, )][DBLP]

  172. An embedded infrastructure of debug and trace interface for the DSP platform. [Citation Graph (, )][DBLP]

  173. IntellBatt: towards smarter battery design. [Citation Graph (, )][DBLP]

  174. A power and temperature aware DRAM architecture. [Citation Graph (, )][DBLP]

  175. Phase-adjustable error detection flip-flops with 2-stage hold driven optimization and slack based grouping scheme for dynamic voltage scaling. [Citation Graph (, )][DBLP]

  176. Temperature management in multiprocessor SoCs using online learning. [Citation Graph (, )][DBLP]

  177. DVFS in loop accelerators using BLADES. [Citation Graph (, )][DBLP]

  178. DFM in practice: hit or hype? [Citation Graph (, )][DBLP]

  179. Statistical modeling and simulation of threshold variation under dopant fluctuations and line-edge roughness. [Citation Graph (, )][DBLP]

  180. Efficient algorithm for the computation of on-chip capacitance sensitivities with respect to a large set of parameters. [Citation Graph (, )][DBLP]

  181. Leakage power reduction using stress-enhanced layouts. [Citation Graph (, )][DBLP]

  182. A fast, analytical estimator for the SEU-induced pulse width in combinational designs. [Citation Graph (, )][DBLP]

  183. On the role of timing masking in reliable logic circuit design. [Citation Graph (, )][DBLP]

  184. Study of the effects of MBUs on the reliability of a 150 nm SRAM device. [Citation Graph (, )][DBLP]

  185. Partial order reduction for scalable testing of systemC TLM designs. [Citation Graph (, )][DBLP]

  186. Construction of concrete verification models from C++. [Citation Graph (, )][DBLP]

  187. Predictive runtime verification of multi-processor SoCs in SystemC. [Citation Graph (, )][DBLP]

  188. Automated hardware-independent scenario identification. [Citation Graph (, )][DBLP]

  189. Predictive design space exploration using genetically programmed response surfaces. [Citation Graph (, )][DBLP]

  190. Efficient system design space exploration using machine learning techniques. [Citation Graph (, )][DBLP]

  191. Improve simulation efficiency using statistical benchmark subsetting: an ImplantBench case study. [Citation Graph (, )][DBLP]

  192. Modeling crosstalk in statistical static timing analysis. [Citation Graph (, )][DBLP]

  193. Power gating scheduling for power/ground noise reduction. [Citation Graph (, )][DBLP]

  194. Forbidden transition free crosstalk avoidance CODEC design. [Citation Graph (, )][DBLP]

  195. Custom is from Venus and synthesis from Mars. [Citation Graph (, )][DBLP]

System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
System created by [] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002