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Conferences in DBLP

Design Automation Conference (DAC) (dac)
2009 (conf/dac/2009)


  1. System prototypes: virtual, hardware or hybrid? [Citation Graph (, )][DBLP]


  2. Circuit techniques for dynamic variation tolerance. [Citation Graph (, )][DBLP]


  3. Enabling adaptability through elastic clocks. [Citation Graph (, )][DBLP]


  4. Addressing design margins through error-tolerant circuits. [Citation Graph (, )][DBLP]


  5. Worst-case aggressor-victim alignment with current-source driver models. [Citation Graph (, )][DBLP]


  6. A moment-based effective characterization waveform for static timing analysis. [Citation Graph (, )][DBLP]


  7. A false-path aware formal static timing analyzer considering simultaneous input transitions. [Citation Graph (, )][DBLP]


  8. Way Stealing: cache-assisted automatic instruction set extensions. [Citation Graph (, )][DBLP]


  9. SysCOLA: a framework for co-development of automotive software and system platform. [Citation Graph (, )][DBLP]


  10. Designing heterogeneous ECU networks via compact architecture encoding and hybrid timing analysis. [Citation Graph (, )][DBLP]


  11. Optimizing throughput of power- and thermal-constrained multicore processors using DVFS and per-core power-gating. [Citation Graph (, )][DBLP]


  12. Design automation for a 3DIC FFT processor for synthetic aperture radar: a case study. [Citation Graph (, )][DBLP]


  13. Selective wordline voltage boosting for caches to manage yield under process variations. [Citation Graph (, )][DBLP]


  14. Double patterning lithography friendly detailed routing with redundant via consideration. [Citation Graph (, )][DBLP]


  15. Use of lithography simulation for the calibration of equation-based design rule checks. [Citation Graph (, )][DBLP]


  16. Carbon nanotube circuits in the presence of carbon nanotube density variations. [Citation Graph (, )][DBLP]


  17. Decoding nanowire arrays fabricated with the multi-spacer patterning technique. [Citation Graph (, )][DBLP]


  18. Boolean logic function synthesis for generalised threshold gate circuits. [Citation Graph (, )][DBLP]


  19. Improving STT MRAM storage density through smaller-than-worst-case transistor sizing. [Citation Graph (, )][DBLP]


  20. EDA in flux: should I stay or should I go? [Citation Graph (, )][DBLP]


  21. Design perspectives on 22nm CMOS and beyond. [Citation Graph (, )][DBLP]


  22. Creating an affordable 22nm node using design-lithography co-optimization. [Citation Graph (, )][DBLP]


  23. Device/circuit interactions at 22nm technology node. [Citation Graph (, )][DBLP]


  24. Beyond innovation: dealing with the risks and complexity of processor design in 22nm. [Citation Graph (, )][DBLP]


  25. Physically justifiable die-level modeling of spatial variation in view of systematic across wafer variability. [Citation Graph (, )][DBLP]


  26. A Gaussian mixture model for statistical timing analysis. [Citation Graph (, )][DBLP]


  27. A stochastic jitter model for analyzing digital timing-recovery circuits. [Citation Graph (, )][DBLP]


  28. Statistical ordering of correlated timing quantities and its application for path ranking. [Citation Graph (, )][DBLP]


  29. A parametric approach for handling local variation effects in timing analysis. [Citation Graph (, )][DBLP]


  30. Non-intrusive dynamic application profiling for multitasked applications. [Citation Graph (, )][DBLP]


  31. A trace-capable instruction cache for cost efficient real-time program trace compression in SoC. [Citation Graph (, )][DBLP]


  32. Generating test programs to cover pipeline interactions. [Citation Graph (, )][DBLP]


  33. NUDA: a non-uniform debugging architecture and non-intrusive race detection for many-core. [Citation Graph (, )][DBLP]


  34. Efficient smart sampling based full-chip leakage analysis for intra-die variation considering state dependence. [Citation Graph (, )][DBLP]


  35. Resurrecting infeasible clock-gating functions. [Citation Graph (, )][DBLP]


  36. Low power gated bus synthesis using shortest-path Steiner graph for system-on-chip communications. [Citation Graph (, )][DBLP]


  37. ActivaSC: a highly efficient and non-intrusive extension for activity-based analysis of SystemC models. [Citation Graph (, )][DBLP]


  38. GPU friendly fast Poisson solver for structured power grid network analysis. [Citation Graph (, )][DBLP]


  39. Fast vectorless power grid verification using an approximate inverse technique. [Citation Graph (, )][DBLP]


  40. Computing bounds for fault tolerance using formal techniques. [Citation Graph (, )][DBLP]


  41. Clock skew optimization via wiresizing for timing sign-off covering all process corners. [Citation Graph (, )][DBLP]


  42. Moore's Law: another casualty of the financial meltdown? [Citation Graph (, )][DBLP]


  43. Holistic verification: myth or magic bullet? [Citation Graph (, )][DBLP]


  44. Verification problems in reusing internal design components. [Citation Graph (, )][DBLP]


  45. Exploiting "architecture for verification" to streamline the verification process. [Citation Graph (, )][DBLP]


  46. Role of the verification team throughout the ASIC development life cycle. [Citation Graph (, )][DBLP]


  47. An efficient approach for system-level timing simulation of compiler-optimized embedded software. [Citation Graph (, )][DBLP]


  48. MPTLsim: a simulator for X86 multicore processors. [Citation Graph (, )][DBLP]


  49. Trace-driven workload simulation method for Multiprocessor System-On-Chips. [Citation Graph (, )][DBLP]


  50. Analysis and mitigation of process variation impacts on Power-Attack Tolerance. [Citation Graph (, )][DBLP]


  51. Evaluating design trade-offs in customizable processors. [Citation Graph (, )][DBLP]


  52. A design flow for application specific heterogeneous pipelined multiprocessor systems. [Citation Graph (, )][DBLP]


  53. Xquasher: a tool for efficient computation of multiple linear expressions. [Citation Graph (, )][DBLP]


  54. ILP-based pin-count aware design methodology for microfluidic biochips. [Citation Graph (, )][DBLP]


  55. O-Router: an optical routing framework for low power on-chip silicon nano-photonic integration. [Citation Graph (, )][DBLP]


  56. BDD-based synthesis of reversible logic for large functions. [Citation Graph (, )][DBLP]


  57. Soft connections: addressing the hardware-design modularity problem. [Citation Graph (, )][DBLP]


  58. A computing origami: folding streams in FPGAs. [Citation Graph (, )][DBLP]


  59. Retiming and recycling for elastic systems with early evaluation. [Citation Graph (, )][DBLP]


  60. Speculation in elastic systems. [Citation Graph (, )][DBLP]


  61. DFM: don't care or competitive weapon? [Citation Graph (, )][DBLP]


  62. The semiconductor industry's nanoelectronics research initiative: motivation and challenges. [Citation Graph (, )][DBLP]


  63. Single-electron devices for ubiquitous and secure computing applications. [Citation Graph (, )][DBLP]


  64. Digital VLSI logic technology using Carbon Nanotube FETs: frequently asked questions. [Citation Graph (, )][DBLP]


  65. CMOS scaling beyond 32nm: challenges and opportunities. [Citation Graph (, )][DBLP]


  66. An O(n log n) path-based obstacle-avoiding algorithm for rectilinear Steiner tree construction. [Citation Graph (, )][DBLP]


  67. GRIP: scalable 3D global routing using integer programming. [Citation Graph (, )][DBLP]


  68. Automatic bus planner for dense PCBs. [Citation Graph (, )][DBLP]


  69. A correct network flow model for escape routing. [Citation Graph (, )][DBLP]


  70. Flip-chip routing with unified area-I/O pad assignments for package-board co-design. [Citation Graph (, )][DBLP]


  71. Statistical multilayer process space coverage for at-speed test. [Citation Graph (, )][DBLP]


  72. Speedpath analysis based on hypothesis pruning and ranking. [Citation Graph (, )][DBLP]


  73. Interconnection fabric design for tracing signals in post-silicon validation. [Citation Graph (, )][DBLP]


  74. Online cache state dumping for processor debug. [Citation Graph (, )][DBLP]


  75. Finding deterministic solution from underdetermined equation: large-scale performance modeling by least angle regression. [Citation Graph (, )][DBLP]


  76. A robust and efficient harmonic balance (HB) using direct solution of HB Jacobian. [Citation Graph (, )][DBLP]


  77. Stochastic steady-state and AC analyses of mixed-signal systems. [Citation Graph (, )][DBLP]


  78. Parallelizable stable explicit numerical integration for efficient circuit simulation. [Citation Graph (, )][DBLP]


  79. Efficient design-specific worst-case corner extraction for integrated circuits. [Citation Graph (, )][DBLP]


  80. Timing-driven optimization using lookahead logic circuits. [Citation Graph (, )][DBLP]


  81. Simulation and SAT-based Boolean matching for large Boolean networks. [Citation Graph (, )][DBLP]


  82. New spare cell design for IR drop minimization in Engineering Change Order. [Citation Graph (, )][DBLP]


  83. Matching-based minimum-cost spare cell selection for design changes. [Citation Graph (, )][DBLP]


  84. Handling don't-care conditions in high-level synthesis and application for reducing initialized registers. [Citation Graph (, )][DBLP]


  85. Oil fields, hedge funds, and drugs. [Citation Graph (, )][DBLP]


  86. Human computation. [Citation Graph (, )][DBLP]


  87. How to make computers that work like the brain. [Citation Graph (, )][DBLP]


  88. A fully polynomial time approximation scheme for timing driven minimum cost buffer insertion. [Citation Graph (, )][DBLP]


  89. Spare-cell-aware multilevel analytical placement. [Citation Graph (, )][DBLP]


  90. Handling complexities in modern large-scale mixed-size placement. [Citation Graph (, )][DBLP]


  91. RegPlace: a high quality open-source placement framework for structured ASICs. [Citation Graph (, )][DBLP]


  92. A novel verification technique to uncover out-of-order DUV behaviors. [Citation Graph (, )][DBLP]


  93. Shortening the verification cycle with synthesizable abstract models. [Citation Graph (, )][DBLP]


  94. Non-cycle-accurate sequential equivalence checking. [Citation Graph (, )][DBLP]


  95. Regression verification. [Citation Graph (, )][DBLP]


  96. Accurate temperature estimation using noisy thermal sensors. [Citation Graph (, )][DBLP]


  97. Spectral techniques for high-resolution thermal characterization with limited sensor data. [Citation Graph (, )][DBLP]


  98. Dynamic thermal management via architectural adaptation. [Citation Graph (, )][DBLP]


  99. On-line thermal aware dynamic voltage scaling for energy optimization with frequency/temperature dependency consideration. [Citation Graph (, )][DBLP]


  100. SRAM parametric failure analysis. [Citation Graph (, )][DBLP]


  101. Soft error optimization of standard cell circuits based on gate sizing and multi-objective genetic algorithm. [Citation Graph (, )][DBLP]


  102. Improving testability and soft-error resilience through retiming. [Citation Graph (, )][DBLP]


  103. Statistical reliability analysis under process variation and aging effects. [Citation Graph (, )][DBLP]


  104. Guess, solder, measure, repeat: how do I get my mixed-signal chip right? [Citation Graph (, )][DBLP]


  105. The Cilk++ concurrency platform. [Citation Graph (, )][DBLP]


  106. Misleading performance claims in parallel computations. [Citation Graph (, )][DBLP]


  107. Massively parallel processing: it's déjà vu all over again. [Citation Graph (, )][DBLP]


  108. Provably good and practically efficient algorithms for CMP dummy fill. [Citation Graph (, )][DBLP]


  109. Predicting variability in nanoscale lithography processes. [Citation Graph (, )][DBLP]


  110. Variability analysis under layout pattern-dependent rapid-thermal annealing process. [Citation Graph (, )][DBLP]


  111. Event-driven gate-level simulation with GP-GPUs. [Citation Graph (, )][DBLP]


  112. Efficient SAT solving for non-clausal formulas using DPLL, graphs, and watched cuts. [Citation Graph (, )][DBLP]


  113. Constraints in one-to-many concretization for abstraction refinement. [Citation Graph (, )][DBLP]


  114. Spectrum: a hybrid nanophotonic-electric on-chip network. [Citation Graph (, )][DBLP]


  115. Exploring serial vertical interconnects for 3D ICs. [Citation Graph (, )][DBLP]


  116. No cache-coherence: a single-cycle ring interconnection for multi-core L1-NUCA sharing on 3D chips. [Citation Graph (, )][DBLP]


  117. Thermal-driven analog placement considering device matching. [Citation Graph (, )][DBLP]


  118. Yield-driven iterative robust circuit optimization algorithm. [Citation Graph (, )][DBLP]


  119. Contract-based system-level composition of analog circuits. [Citation Graph (, )][DBLP]


  120. Serial reconfigurable mismatch-tolerant clock distribution. [Citation Graph (, )][DBLP]


  121. Thermal-aware data flow analysis. [Citation Graph (, )][DBLP]


  122. Nanoscale digital computation through percolation. [Citation Graph (, )][DBLP]


  123. A learning digital computer. [Citation Graph (, )][DBLP]


  124. Programmable neural processing on a smartdust. [Citation Graph (, )][DBLP]


  125. Human computing for EDA. [Citation Graph (, )][DBLP]


  126. Synthesizing hardware from sketches. [Citation Graph (, )][DBLP]


  127. Endosymbiotic computing: enabling surrogate GUI and cyber-physical connectivity. [Citation Graph (, )][DBLP]


  128. Debugging from high level down to gate level. [Citation Graph (, )][DBLP]


  129. The day Sherlock Holmes decided to do EDA. [Citation Graph (, )][DBLP]


  130. Debugging strategies for mere mortals. [Citation Graph (, )][DBLP]


  131. MAGENTA: transaction-based statistical micro-architectural root-cause analysis. [Citation Graph (, )][DBLP]


  132. Untwist your brain: efficient debugging and diagnosis of complex assertions. [Citation Graph (, )][DBLP]


  133. Beyond verification: leveraging formal for debugging. [Citation Graph (, )][DBLP]


  134. Power modeling of graphical user interfaces on OLED displays. [Citation Graph (, )][DBLP]


  135. Energy-aware error control coding for Flash memories. [Citation Graph (, )][DBLP]


  136. PDRAM: a hybrid PRAM and DRAM main memory system. [Citation Graph (, )][DBLP]


  137. A voltage-scalable & process variation resilient hybrid SRAM architecture for MPEG-4 video processors. [Citation Graph (, )][DBLP]


  138. A physical unclonable function defined using power distribution system equivalent resistance variations. [Citation Graph (, )][DBLP]


  139. Hardware authentication leveraging performance limits in detailed simulations and emulations. [Citation Graph (, )][DBLP]


  140. Hardware Trojan horse detection using gate-level characterization. [Citation Graph (, )][DBLP]


  141. Process variation characterization of chip-level multiprocessors. [Citation Graph (, )][DBLP]


  142. Information hiding for trusted system design. [Citation Graph (, )][DBLP]


  143. On systematic illegal state identification for pseudo-functional testing. [Citation Graph (, )][DBLP]


  144. Automated failure population creation for validating integrated circuit diagnosis methods. [Citation Graph (, )][DBLP]


  145. Fault models for embedded-DRAM macros. [Citation Graph (, )][DBLP]


  146. Adaptive test elimination for analog/RF circuits. [Citation Graph (, )][DBLP]


  147. WCET-aware register allocation based on graph coloring. [Citation Graph (, )][DBLP]


  148. Optimal static WCET-aware scratchpad allocation of program code. [Citation Graph (, )][DBLP]


  149. A real-time program trace compressor utilizing double move-to-front method. [Citation Graph (, )][DBLP]


  150. Heterogeneous code cache: using scratchpad and main memory in dynamic binary translators. [Citation Graph (, )][DBLP]


  151. From milliwatts to megawatts: system level power challenge. [Citation Graph (, )][DBLP]


  152. A direct integral-equation solver of linear complexity for large-scale 3D capacitance and impedance extraction. [Citation Graph (, )][DBLP]


  153. Variational capacitance extraction of on-chip interconnects based on continuous surface model. [Citation Graph (, )][DBLP]


  154. PiCAP: a parallel and incremental capacitance extraction considering stochastic process variation. [Citation Graph (, )][DBLP]


  155. An efficient resistance sensitivity extraction algorithm for conductors of arbitrary shapes. [Citation Graph (, )][DBLP]


  156. Throughput optimal task allocation under thermal constraints for multi-core processors. [Citation Graph (, )][DBLP]


  157. An adaptive scheduling and voltage/frequency selection algorithm for real-time energy harvesting systems. [Citation Graph (, )][DBLP]


  158. Software-assisted hardware reliability: abstracting circuit-level challenges to the software stack. [Citation Graph (, )][DBLP]


  159. Simultaneous clock buffer sizing and polarity assignment for power/ground noise minimization. [Citation Graph (, )][DBLP]


  160. An SDRAM-aware router for Networks-on-Chip. [Citation Graph (, )][DBLP]


  161. Multiprocessor System-on-Chip designs with active memory processors for higher memory efficiency. [Citation Graph (, )][DBLP]


  162. Vicis: a reliable network for unreliable silicon. [Citation Graph (, )][DBLP]


  163. Technology-driven limits on DVFS controllability of multiple voltage-frequency island designs: a system-level perspective. [Citation Graph (, )][DBLP]


  164. NoC topology synthesis for supporting shutdown of voltage islands in SoCs. [Citation Graph (, )][DBLP]


  165. Hierarchical reconfigurable computing arrays for efficient CGRA-based embedded systems. [Citation Graph (, )][DBLP]


  166. Multicore parallel min-cost flow algorithm for CAD applications. [Citation Graph (, )][DBLP]


  167. FPGA-targeted high-level binding algorithm for power and area reduction with glitch-estimation. [Citation Graph (, )][DBLP]


  168. FPGA-based accelerator for the verification of leading-edge wireless systems. [Citation Graph (, )][DBLP]


  169. Transmuting coprocessors: dynamic loading of FPGA coprocessors. [Citation Graph (, )][DBLP]


  170. Dynamic thread and data mapping for NoC based CMPs. [Citation Graph (, )][DBLP]


  171. A commitment-based management strategy for the performance and reliability enhancement of flash-memory storage systems. [Citation Graph (, )][DBLP]


  172. Quality-driven synthesis of embedded multi-mode control systems. [Citation Graph (, )][DBLP]


  173. Context-sensitive timing analysis of Esterel programs. [Citation Graph (, )][DBLP]


  174. Scheduling the FlexRay bus using optimization techniques. [Citation Graph (, )][DBLP]


  175. The wild west: conquest of complex hardware-dependent software design. [Citation Graph (, )][DBLP]


  176. Internet-in-a-Box: emulating datacenter network architectures using FPGAs. [Citation Graph (, )][DBLP]


  177. Sustainable data centers: enabled by supply and demand side management. [Citation Graph (, )][DBLP]


  178. Green data centers and hot chips. [Citation Graph (, )][DBLP]


  179. Optimum LDPC decoder: a memory architecture problem. [Citation Graph (, )][DBLP]


  180. A DVS-based pipelined reconfigurable instruction memory. [Citation Graph (, )][DBLP]


  181. LICT: left-uncompressed instructions compression technique to improve the decoding performance of VLIW processors. [Citation Graph (, )][DBLP]


  182. Hierarchical architecture of flash-based storage systems for high performance and durability. [Citation Graph (, )][DBLP]


  183. Reduction techniques for synchronous dataflow graphs. [Citation Graph (, )][DBLP]


  184. A parameterized compositional multi-dimensional multiple-choice knapsack heuristic for CMP run-time management. [Citation Graph (, )][DBLP]


  185. Mode grouping for more effective generalized scheduling of dynamic dataflow applications. [Citation Graph (, )][DBLP]


  186. Efficient program scheduling for heterogeneous multi-core processors. [Citation Graph (, )][DBLP]


  187. Polynomial datapath optimization using partitioning and compensation heuristics. [Citation Graph (, )][DBLP]


  188. Register allocation for high-level synthesis using dual supply voltages. [Citation Graph (, )][DBLP]


  189. GPU-based parallelization for fast circuit optimization. [Citation Graph (, )][DBLP]


  190. Architectural assessment of design techniques to improve speed and robustness in embedded microprocessors. [Citation Graph (, )][DBLP]


  191. ARMS - automatic residue-minimization based sampling for multi-point modeling techniques. [Citation Graph (, )][DBLP]


  192. An efficient passivity test for descriptor systems via canonical projector techniques. [Citation Graph (, )][DBLP]


  193. A parameterized mask model for lithography simulation. [Citation Graph (, )][DBLP]

NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
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for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002