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Conferences in DBLP

Design Automation Conference (DAC) (dac)
2010 (conf/dac/2010)


  1. EDA challenges and options: investing for the future. [Citation Graph (, )][DBLP]


  2. Post-silicon validation challenges: how EDA and academia can help. [Citation Graph (, )][DBLP]


  3. Post-silicon is too late avoiding the $50 million paperweight starts with validated designs. [Citation Graph (, )][DBLP]


  4. Post-silicon validation opportunities, challenges and recent advances. [Citation Graph (, )][DBLP]


  5. A mixed-mode vector-based dataflow approach for modeling and simulating LTE physical layer. [Citation Graph (, )][DBLP]


  6. Abstraction of RTL IPs into embedded software. [Citation Graph (, )][DBLP]


  7. Online SystemC emulation acceleration. [Citation Graph (, )][DBLP]


  8. LATA: a latency and throughput-aware packet processing system. [Citation Graph (, )][DBLP]


  9. A probabilistic and energy-efficient scheduling approach for online application in real-time systems. [Citation Graph (, )][DBLP]


  10. Timing analysis of esterel programs on general-purpose multiprocessors. [Citation Graph (, )][DBLP]


  11. An effective GPU implementation of breadth-first search. [Citation Graph (, )][DBLP]


  12. Thermal monitoring of real processors: techniques for sensor allocation and full characterization. [Citation Graph (, )][DBLP]


  13. Consistent runtime thermal prediction and control through workload phase detection. [Citation Graph (, )][DBLP]


  14. Adaptive and autonomous thermal tracking for high performance computing systems. [Citation Graph (, )][DBLP]


  15. Non-uniform clock mesh optimization with linear programming buffer insertion. [Citation Graph (, )][DBLP]


  16. Fast timing-model independent buffered clock-tree synthesis. [Citation Graph (, )][DBLP]


  17. Clock tree synthesis under aggressive buffer insertion. [Citation Graph (, )][DBLP]


  18. Global routing and track assignment for flip-chip designs. [Citation Graph (, )][DBLP]


  19. Bridging pre-silicon verification and post-silicon validation. [Citation Graph (, )][DBLP]


  20. Compilation and virtualization in the HiPEAC vision. [Citation Graph (, )][DBLP]


  21. Processor virtualization and split compilation for heterogeneous multicore embedded systems. [Citation Graph (, )][DBLP]


  22. Fine-grained I/O access control based on Xen virtualization for 3G/4G mobile devices. [Citation Graph (, )][DBLP]


  23. Device hypervisors. [Citation Graph (, )][DBLP]


  24. A correlation-based design space exploration methodology for multi-processor systems-on-chip. [Citation Graph (, )][DBLP]


  25. Cost-aware three-dimensional (3D) many-core multiprocessor design. [Citation Graph (, )][DBLP]


  26. Off-chip memory bandwidth minimization through cache partitioning for multi-core platforms. [Citation Graph (, )][DBLP]


  27. Virtual prototyper (ViPro): an early design space exploration and optimization tool for SRAM designers. [Citation Graph (, )][DBLP]


  28. Quantifying and coping with parametric variations in 3D-stacked microarchitectures. [Citation Graph (, )][DBLP]


  29. Cost-driven 3D integration with interconnect layers. [Citation Graph (, )][DBLP]


  30. A multilayer nanophotonic interconnection network for on-chip many-core communications. [Citation Graph (, )][DBLP]


  31. Virtual channels vs. multiple physical networks: a comparative analysis. [Citation Graph (, )][DBLP]


  32. An efficient dynamically reconfigurable on-chip network architecture. [Citation Graph (, )][DBLP]


  33. An AIG-Based QBF-solver using SAT for preprocessing. [Citation Graph (, )][DBLP]


  34. Analyzing k-step induction to compute invariants for SAT-based property checking. [Citation Graph (, )][DBLP]


  35. Coverage in interpolation-based model checking. [Citation Graph (, )][DBLP]


  36. An efficient algorithm to verify generalized false paths. [Citation Graph (, )][DBLP]


  37. A parallel integer programming approach to global routing. [Citation Graph (, )][DBLP]


  38. Multi-threaded collision-aware global routing with bounded-length maze routing. [Citation Graph (, )][DBLP]


  39. Two-sided single-detour untangling for bus routing. [Citation Graph (, )][DBLP]


  40. An optimal algorithm for finding disjoint rectangles and its application to PCB routing. [Citation Graph (, )][DBLP]


  41. Who solves the variability problem? [Citation Graph (, )][DBLP]


  42. Joint DAC/IWBDA special session engineering biology: fundamentals and applications. [Citation Graph (, )][DBLP]


  43. Gate-level characterization: foundations and hardware security applications. [Citation Graph (, )][DBLP]


  44. SCEMIT: a systemc error and mutation injection tool. [Citation Graph (, )][DBLP]


  45. Towards scalable system-level reliability analysis. [Citation Graph (, )][DBLP]


  46. Quality metric evaluation of a physical unclonable function derived from an IC's power distribution system. [Citation Graph (, )][DBLP]


  47. Theoretical analysis of gate level information flow tracking. [Citation Graph (, )][DBLP]


  48. Exploiting finite precision information to guide data-flow mapping. [Citation Graph (, )][DBLP]


  49. Robust design methods for hardware accelerators for iterative algorithms in scientific computing. [Citation Graph (, )][DBLP]


  50. New model-driven design and generation of multi-facet arbiters part I: from the design model to the architecture model. [Citation Graph (, )][DBLP]


  51. Bayesian virtual probe: minimizing variation characterization cost for nanoscale IC technologies via Bayesian inference. [Citation Graph (, )][DBLP]


  52. Speedpath analysis under parametric timing models. [Citation Graph (, )][DBLP]


  53. Post-silicon diagnosis of segments of failing speedpaths due to manufacturing variations. [Citation Graph (, )][DBLP]


  54. Pulsed-latch aware placement for timing-integrity optimization. [Citation Graph (, )][DBLP]


  55. History-based VLSI legalization using network flow. [Citation Graph (, )][DBLP]


  56. Performance-driven analog placement considering boundary constraint. [Citation Graph (, )][DBLP]


  57. 3-D stacked die: now or future? [Citation Graph (, )][DBLP]


  58. Networks on Chips: from research to products. [Citation Graph (, )][DBLP]


  59. The aethereal network on chip after ten years: goals, evolution, lessons, and future. [Citation Graph (, )][DBLP]


  60. The evolution of SOC interconnect and how NOC fits within it. [Citation Graph (, )][DBLP]


  61. Automatic multithreaded pipeline synthesis from transactional datapath specifications. [Citation Graph (, )][DBLP]


  62. On the costs and benefits of stochasticity in stream processing. [Citation Graph (, )][DBLP]


  63. Performance yield-driven task allocation and scheduling for MPSoCs under process variation. [Citation Graph (, )][DBLP]


  64. Worst-case response time analysis of resource access models in multi-core systems. [Citation Graph (, )][DBLP]


  65. A new IP lookup cache for high performance IP routers. [Citation Graph (, )][DBLP]


  66. Instruction cache locking using temporal reuse profile. [Citation Graph (, )][DBLP]


  67. Reducing write activities on non-volatile memories in embedded CMPs via data migration and recomputation. [Citation Graph (, )][DBLP]


  68. SCUD: a fast single-pass L1 cache simulation approach for embedded processors with round-robin replacement policy. [Citation Graph (, )][DBLP]


  69. Fully X-tolerant, very high scan compression. [Citation Graph (, )][DBLP]


  70. BLoG: post-silicon bug localization in processors using bug localization graphs. [Citation Graph (, )][DBLP]


  71. Classification rule learning using subgroup discovery of cross-domain attributes responsible for design-silicon mismatch. [Citation Graph (, )][DBLP]


  72. Efficient fault simulation on many-core processors. [Citation Graph (, )][DBLP]


  73. Representative path selection for post-silicon timing prediction under variability. [Citation Graph (, )][DBLP]


  74. QuickYield: an efficient global-search based parametric yield estimation with performance constraints. [Citation Graph (, )][DBLP]


  75. Double patterning lithography aware gridless detailed routing with innovative conflict graph. [Citation Graph (, )][DBLP]


  76. Frequency domain decomposition of layouts for double dipole lithography. [Citation Graph (, )][DBLP]


  77. Compact modeling and robust layout optimization for contacts in deep sub-wavelength lithography. [Citation Graph (, )][DBLP]


  78. Does IC design have a future in the clouds? [Citation Graph (, )][DBLP]


  79. Automated compact dynamical modeling: an enabling tool for analog designers. [Citation Graph (, )][DBLP]


  80. Model-based functional verification. [Citation Graph (, )][DBLP]


  81. Fortifying analog models with equivalence checking and coverage analysis. [Citation Graph (, )][DBLP]


  82. Automated modeling and emulation of interconnect designs for many-core chip multiprocessors. [Citation Graph (, )][DBLP]


  83. Trace-driven optimization of networks-on-chip configurations. [Citation Graph (, )][DBLP]


  84. ACES: application-specific cycle elimination and splitting for deadlock-free routing on irregular network-on-chip. [Citation Graph (, )][DBLP]


  85. NTPT: on the end-to-end traffic prediction in the on-chip networks. [Citation Graph (, )][DBLP]


  86. Application-aware NoC design for efficient SDRAM access. [Citation Graph (, )][DBLP]


  87. Embedded memory binding in FPGAs. [Citation Graph (, )][DBLP]


  88. RAMP gold: an FPGA-based architecture simulator for multiprocessors. [Citation Graph (, )][DBLP]


  89. Rewiring for robustness. [Citation Graph (, )][DBLP]


  90. Efficient tail estimation for massive correlated log-normal sums: with applications in statistical leakage analysis. [Citation Graph (, )][DBLP]


  91. A linear algorithm for full-chip statistical leakage power analysis considering weak spatial correlation. [Citation Graph (, )][DBLP]


  92. Synthesis and implementation of active mode power gating circuits. [Citation Graph (, )][DBLP]


  93. Leakage-aware dynamic scheduling for real-time adaptive applications on multiprocessor systems. [Citation Graph (, )][DBLP]


  94. BooM: a decision procedure for boolean matching with abstraction and dynamic learning. [Citation Graph (, )][DBLP]


  95. Node addition and removal in the presence of don't cares. [Citation Graph (, )][DBLP]


  96. ECR: a low complexity generalized error cancellation rewiring scheme. [Citation Graph (, )][DBLP]


  97. LUT-based FPGA technology mapping for reliability. [Citation Graph (, )][DBLP]


  98. What's cool for the future of ultra low power designs? [Citation Graph (, )][DBLP]


  99. Verification for fault tolerance of the IBM system z microprocessor. [Citation Graph (, )][DBLP]


  100. Formal modeling and reasoning for reliability analysis. [Citation Graph (, )][DBLP]


  101. Using introspective software-based testing for post-silicon debug and repair. [Citation Graph (, )][DBLP]


  102. Xetal-Pro: an ultra-low energy and high throughput SIMD processor. [Citation Graph (, )][DBLP]


  103. A framework for automatic parallelization, static and dynamic memory optimization in MPSoC platforms. [Citation Graph (, )][DBLP]


  104. Scalable effort hardware design: exploiting algorithmic resilience for energy efficiency. [Citation Graph (, )][DBLP]


  105. Parallel program performance modeling for runtime optimization of multi-algorithm circuit simulation. [Citation Graph (, )][DBLP]


  106. Separatrices in high-dimensional state space: system-theoretical tangent computation and application to SRAM dynamic stability analysis. [Citation Graph (, )][DBLP]


  107. A robust periodic arnoldi shooting algorithm for efficient analysis of large-scale RF/MM ICs. [Citation Graph (, )][DBLP]


  108. Distributed task migration for thermal management in many-core systems. [Citation Graph (, )][DBLP]


  109. Thermal aware task sequencing on embedded processors. [Citation Graph (, )][DBLP]


  110. A framework for optimizing thermoelectric active cooling systems. [Citation Graph (, )][DBLP]


  111. Eyecharts: constructive benchmarking of gate sizing heuristics. [Citation Graph (, )][DBLP]


  112. Detecting tangled logic structures in VLSI netlists. [Citation Graph (, )][DBLP]


  113. Lattice-based computation of Boolean functions. [Citation Graph (, )][DBLP]


  114. A novel optimal single constant multiplication algorithm. [Citation Graph (, )][DBLP]


  115. Education panel: designing the always connected car of the future. [Citation Graph (, )][DBLP]


  116. Find your flow: increasing flow experience by designing "human" embedded systems. [Citation Graph (, )][DBLP]


  117. Electronic design automation for social networks. [Citation Graph (, )][DBLP]


  118. Real time emulations: foundation and applications. [Citation Graph (, )][DBLP]


  119. Network on chip design and optimization using specialized influence models. [Citation Graph (, )][DBLP]


  120. Circuit modeling for practical many-core architecture design exploration. [Citation Graph (, )][DBLP]


  121. Hierarchical hybrid power supply networks. [Citation Graph (, )][DBLP]


  122. Detachable nano-carbon chip with ultra low power. [Citation Graph (, )][DBLP]


  123. Synthesis of trustable ICs using untrusted CAD tools. [Citation Graph (, )][DBLP]


  124. Synchronization of washing operations with droplet routing for cross-contamination avoidance in digital microfluidic biochips. [Citation Graph (, )][DBLP]


  125. Cross-contamination aware design methodology for pin-constrained digital microfluidic biochips. [Citation Graph (, )][DBLP]


  126. Reducing the number of lines in reversible circuits. [Citation Graph (, )][DBLP]


  127. Synthesis of the optimal 4-bit reversible circuits. [Citation Graph (, )][DBLP]


  128. Crosstalk noise and bit error rate analysis for optical network-on-chip. [Citation Graph (, )][DBLP]


  129. Parallel multigrid preconditioning on graphics processing units (GPUs) for robust power grid analysis. [Citation Graph (, )][DBLP]


  130. Stochastic dominant singular vectors method for variation-aware extraction. [Citation Graph (, )][DBLP]


  131. Closed-form modeling of layout-dependent mechanical stress. [Citation Graph (, )][DBLP]


  132. Generating parametric models from tabulated data. [Citation Graph (, )][DBLP]


  133. MFTI: matrix-format tangential interpolation for modeling multi-port systems. [Citation Graph (, )][DBLP]


  134. A universal state-of-charge algorithm for batteries. [Citation Graph (, )][DBLP]


  135. A complete design-flow for the generation of ultra low-power WSN node architectures based on micro-tasking. [Citation Graph (, )][DBLP]


  136. Stacking SRAM banks for ultra low power standby mode operation. [Citation Graph (, )][DBLP]


  137. PreDVS: preemptive dynamic voltage scaling for real-time systems using approximation scheme. [Citation Graph (, )][DBLP]


  138. In-situ characterization and extraction of SRAM variability. [Citation Graph (, )][DBLP]


  139. A holistic approach for statistical SRAM analysis. [Citation Graph (, )][DBLP]


  140. Clock tree synthesis with pre-bond testability for 3D stacked IC designs. [Citation Graph (, )][DBLP]


  141. An efficient phase detector connection structure for the skew synchronization system. [Citation Graph (, )][DBLP]


  142. What will make your next design experience a much better one? [Citation Graph (, )][DBLP]


  143. Cyber-physical systems: the next computing revolution. [Citation Graph (, )][DBLP]


  144. CPS foundations. [Citation Graph (, )][DBLP]


  145. Medical cyber physical systems. [Citation Graph (, )][DBLP]


  146. Cyber-physical energy systems: focus on smart buildings. [Citation Graph (, )][DBLP]


  147. Scalable specification mining for verification and diagnosis. [Citation Graph (, )][DBLP]


  148. Distributed time, conservative parallel logic simulation on GPUs. [Citation Graph (, )][DBLP]


  149. An efficient test vector generation for checking analog/mixed-signal functional models. [Citation Graph (, )][DBLP]


  150. Leveraging UPF-extracted assertions for modeling and formal verification of architectural power intent. [Citation Graph (, )][DBLP]


  151. Efficient simulation of oscillatory combinational loops. [Citation Graph (, )][DBLP]


  152. Transistor sizing of custom high-performance digital circuits with parametric yield considerations. [Citation Graph (, )][DBLP]


  153. RDE-based transistor-level gate simulation for statistical static timing analysis. [Citation Graph (, )][DBLP]


  154. Efficient smart monte carlo based SSTA on graphics processing units with improved resource utilization. [Citation Graph (, )][DBLP]


  155. Static timing analysis for flexible TFT circuits. [Citation Graph (, )][DBLP]


  156. TSV stress aware timing analysis with applications to 3D-IC layout optimization. [Citation Graph (, )][DBLP]


  157. A system for online power prediction in virtualized environments using Gaussian mixture models. [Citation Graph (, )][DBLP]


  158. Performance and power modeling in a multi-programmed multi-core environment. [Citation Graph (, )][DBLP]


  159. Reliability aware power management for dual-processor real-time embedded systems. [Citation Graph (, )][DBLP]


  160. Recovery-driven design: a power minimization methodology for error-tolerant processor modules. [Citation Graph (, )][DBLP]


  161. Tradeoff analysis and optimization of power delivery networks with on-chip voltage regulation. [Citation Graph (, )][DBLP]


  162. An efficient dual algorithm for vectorless power grid verification under linear current constraints. [Citation Graph (, )][DBLP]


  163. Parallel hierarchical cross entropy optimization for on-chip decap budgeting. [Citation Graph (, )][DBLP]


  164. SRAM-based NBTI/PBTI sensor system design. [Citation Graph (, )][DBLP]


  165. A statistical simulation method for reliability analysis of SRAM core-cells. [Citation Graph (, )][DBLP]


  166. What input-language is the best choice for high level synthesis (HLS)? [Citation Graph (, )][DBLP]


  167. Stochastic computation. [Citation Graph (, )][DBLP]


  168. Best-effort computing: re-thinking parallel software and hardware. [Citation Graph (, )][DBLP]


  169. Hardware that produces bounded rather than exact results. [Citation Graph (, )][DBLP]


  170. Impact of process variations on emerging memristor. [Citation Graph (, )][DBLP]


  171. Reconfigurable multi-function logic based on graphene P-N junctions. [Citation Graph (, )][DBLP]


  172. Carbon nanotube correlation: promising opportunity for CNFET circuit yield enhancement. [Citation Graph (, )][DBLP]


  173. Design and analysis of compact ultra energy-efficient logic gates using laterally-actuated double-electrode NEMS. [Citation Graph (, )][DBLP]


  174. Toward efficient large-scale performance modeling of integrated circuits via multi-mode/multi-corner sparse regression. [Citation Graph (, )][DBLP]


  175. Behavior-level yield enhancement approach for large-scaled analog circuits. [Citation Graph (, )][DBLP]


  176. Generation of yield-embedded Pareto-front for simultaneous optimization of yield and performances. [Citation Graph (, )][DBLP]


  177. Pareto sampling: choosing the right weights by derivative pursuit. [Citation Graph (, )][DBLP]


  178. An error tolerance scheme for 3D CMOS imagers. [Citation Graph (, )][DBLP]


  179. Fast identification of operating current for toggle MRAM by spiral search. [Citation Graph (, )][DBLP]


  180. Exploiting reconfigurability for low-cost in-situ test and monitoring of digital PLLs. [Citation Graph (, )][DBLP]


  181. Smart phone power. [Citation Graph (, )][DBLP]


  182. What's smart about the smart grid? [Citation Graph (, )][DBLP]


  183. On-die power grids: the missing link. [Citation Graph (, )][DBLP]

NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002