The SCEAS System
Navigation Menu

Conferences in DBLP

Design, Automation, and Test in Europe (date)
2008 (conf/date/2008)


  1. Heterogeneous System-level Specification Using SystemC. [Citation Graph (, )][DBLP]


  2. Soft Errors: System Effects, Protection Techniques and Case Studies. [Citation Graph (, )][DBLP]


  3. DfM in the Analogue and Digital World. [Citation Graph (, )][DBLP]


  4. Power Gating for Ultra-low Leakage: Physics, Design, and Analysis. [Citation Graph (, )][DBLP]


  5. System-Level Design and Application Mapping for Wireless and Multimedia MPSoC Architectures. [Citation Graph (, )][DBLP]


  6. Automatically Realising Embedded Systems from High-Level Functional Models. [Citation Graph (, )][DBLP]


  7. Design Variability: Challenges and Solutions at Microarchitecture-Architecture Level. [Citation Graph (, )][DBLP]


  8. Power-Aware Testing and Test Strategies for Low Power Devices. [Citation Graph (, )][DBLP]


  9. Formal Methods in System and MpSoC Performance Analysis and Optimisation. [Citation Graph (, )][DBLP]


  10. From Transistor to PLL - Analogue Design and EDA Methods. [Citation Graph (, )][DBLP]


  11. Design Flows, Communication Based Design and Architectures in Automotive Electronic Systems. [Citation Graph (, )][DBLP]


  12. Designing Micro/Nano Systems for a Safer and Healthier Tomorrow. [Citation Graph (, )][DBLP]


  13. Perspective on Embedded Systems: Challenges, Solutions and Research Priorities. [Citation Graph (, )][DBLP]


  14. Cycle-approximate Retargetable Performance Estimation at the Transaction Level. [Citation Graph (, )][DBLP]


  15. A Method for the Efficient Development of Timed and Untimed Transaction-Level Models of Systems-on-Chip. [Citation Graph (, )][DBLP]


  16. Integrating RTL IPs into TLM Designs Through Automatic Transactor Generation. [Citation Graph (, )][DBLP]


  17. Tailored Solutions for Safety-Installations in the Loetschberg Tunnel - A Project with Importance for the Trans-European Rail Traffic. [Citation Graph (, )][DBLP]


  18. On the Verification of High-Order Constraint Compliance in IC Design. [Citation Graph (, )][DBLP]


  19. Industrial IP Integration Flows based on IP-XACT Standards. [Citation Graph (, )][DBLP]


  20. A Reconfigurable Application Specific Instruction Set Processor for Convolutional and Turbo Decoding in a SDR Environment. [Citation Graph (, )][DBLP]


  21. Using Reconfigurable Logic to Optimise GPU Memory Accesses. [Citation Graph (, )][DBLP]


  22. Cost-and Power Optimized FPGA based System Integration: Methodologies and Integration of a Low-Power Capacity-based Measurement Application on Xilinx FPGAs. [Citation Graph (, )][DBLP]


  23. Design flow for embedded FPGAs based on a flexible architecture template. [Citation Graph (, )][DBLP]


  24. Optimal High-Resolution Spectral Analyzer. [Citation Graph (, )][DBLP]


  25. A General Method to Evaluate RF BIST Techniques Based on Non-parametric Density Estimation. [Citation Graph (, )][DBLP]


  26. Diagnostic Analysis of Static Errors in Multi-Step Analog to Digital Converters. [Citation Graph (, )][DBLP]


  27. Practical Implementation of a Network Analyzer for Analog BIST Applications. [Citation Graph (, )][DBLP]


  28. Quantitative Evaluation in Embedded System Design: Trends in Modeling and Analysis Techniques. [Citation Graph (, )][DBLP]


  29. Quantitative Evaluation in Embedded System Design: Validation of Multiprocessor Multithreaded Architectures. [Citation Graph (, )][DBLP]


  30. Quantitative Evaluation in Embedded System Design: Predicting Battery Lifetime in Mobile Devices. [Citation Graph (, )][DBLP]


  31. A Framework of Stochastic Power Management Using Hidden Markov Model. [Citation Graph (, )][DBLP]


  32. Harvesting Wasted Heat in a Microprocessor Using Thermoelectric Generators: Modeling, Analysis and Measurement. [Citation Graph (, )][DBLP]


  33. An Efficient Solar Energy Harvester for Wireless Sensor Nodes. [Citation Graph (, )][DBLP]


  34. Temperature Control of High-Performance Multi-core Platforms Using Convex Optimization. [Citation Graph (, )][DBLP]


  35. Parametric Throughput Analysis of Synchronous Data Flow Graphs. [Citation Graph (, )][DBLP]


  36. Introducing Preemptive Scheduling in Abstract RTOS Models using Result Oriented Modeling. [Citation Graph (, )][DBLP]


  37. SystemC-based Modelling, Seamless Refinement, and Synthesis of a JPEG 2000 Decoder. [Citation Graph (, )][DBLP]


  38. Modeling and Refining Heterogeneous Systems With SystemC-AMS: Application to WSN. [Citation Graph (, )][DBLP]


  39. Sizing Rules for Bipolar Analog Circuit Design. [Citation Graph (, )][DBLP]


  40. Efficient circuit-level modelling of ballistic CNT using piecewise non-linear approximation of mobile charge density. [Citation Graph (, )][DBLP]


  41. A New Approach for Combining Yield and Performance in Behavioural Models for Analogue Integrated Circuits. [Citation Graph (, )][DBLP]


  42. Symbolic Reliability Analysis and Optimization of ECU Networks. [Citation Graph (, )][DBLP]


  43. Verification of Temporal Properties in Automotive Embedded Software. [Citation Graph (, )][DBLP]


  44. A Novel Approach for EMI Design of Power Electronics. [Citation Graph (, )][DBLP]


  45. Hardware/software architecture of an algorithm for vision-based real-time vehicle detection in dark environments. [Citation Graph (, )][DBLP]


  46. Analysis of The Test Data Volume Reduction Benefit of Modular SOC Testing. [Citation Graph (, )][DBLP]


  47. Test-Architecture Optimization and Test Scheduling for SOCs with Core-Level Expansion of Compressed Test Patterns. [Citation Graph (, )][DBLP]


  48. An novel Methodology for Reducing SoC Test Data Volume on FPGA-based Testers. [Citation Graph (, )][DBLP]


  49. Performance Analysis of SoC Architectures Based on Latency-Rate Servers. [Citation Graph (, )][DBLP]


  50. Slack Allocation Based Co-Synthesis and Optimization of Bus and Memory Architectures for MPSoCs. [Citation Graph (, )][DBLP]


  51. Run-time Spatial Mapping of Streaming Applications to a Heterogeneous Multi-Processor System-on-Chip (MPSOC). [Citation Graph (, )][DBLP]


  52. Architecture Exploration of NAND Flash-based Multimedia Card. [Citation Graph (, )][DBLP]


  53. Resilient Dynamic Power Management under Uncertainty. [Citation Graph (, )][DBLP]


  54. Robust and Low Complexity Rate Control for Solar Powered Sensors. [Citation Graph (, )][DBLP]


  55. Energy Aware Dynamic Voltage and Frequency Selection for Real-Time Systems with Energy Harvesting. [Citation Graph (, )][DBLP]


  56. Dynamic Voltage Scaling of Supply and Body Bias Exploiting Software Runtime Distribution. [Citation Graph (, )][DBLP]


  57. Built-in Clock Skew System for On-line Debug and Repair. [Citation Graph (, )][DBLP]


  58. Analysis and Optimization of the Recessed Probe Launch for High Frequency Measurements of PCB Interconnects. [Citation Graph (, )][DBLP]


  59. On Automated Trigger Event Generation in Post-Silicon Validation. [Citation Graph (, )][DBLP]


  60. Dynamic Round-Robin Task Scheduling to Reduce Cache Misses for Embedded Systems. [Citation Graph (, )][DBLP]


  61. Improving the Efficiency of Run Time Reconfigurable Devices by Configuration Locking. [Citation Graph (, )][DBLP]


  62. Logic Synthesis with Nanowire Crossbar: Reality Check and Standard Cell-based Integration. [Citation Graph (, )][DBLP]


  63. Merged Computation for Whirlpool Hashing. [Citation Graph (, )][DBLP]


  64. Source-Level Timing Annotation and Simulation for a Heterogeneous Multiprocessor. [Citation Graph (, )][DBLP]


  65. Safe Automatic Flight Back and Landing of Aircraft Flight Reconfiguration Function (FRF). [Citation Graph (, )][DBLP]


  66. PWM-Based Test Stimuli Generation for BIST of High Resolution ADCs. [Citation Graph (, )][DBLP]


  67. Temperature-Aware Scheduling and Assignment for Hard Real-Time Applications on MPSoCs. [Citation Graph (, )][DBLP]


  68. A Formal Approach To The Protocol Converter Problem. [Citation Graph (, )][DBLP]


  69. Cache Aware Mapping of Streaming Applications on a Multiprocessor System-on-Chip. [Citation Graph (, )][DBLP]


  70. Synthesizing Synchronous Elastic Flow Networks. [Citation Graph (, )][DBLP]


  71. Periodic Steady-State Analysis Augmented with Design Equality Constraints. [Citation Graph (, )][DBLP]


  72. Analysis of Oscillator Injection Locking by Harmonic Balance Method. [Citation Graph (, )][DBLP]


  73. Model Checking of Analog Systems using an Analog Specification Language. [Citation Graph (, )][DBLP]


  74. Mapping Semantics of CORBA IDL and GIOP to Open Core Protocol for Portability and Interoperability of SDR Waveform Components. [Citation Graph (, )][DBLP]


  75. On the design of tunable fault tolerant circuits on SRAM-based FPGAs for safety critical applications. [Citation Graph (, )][DBLP]


  76. Hot Wire Anemometric MEMS Sensor for Water Flow Monitoring. [Citation Graph (, )][DBLP]


  77. Guiding Circuit Level Fault-Tolerance Design with Statistical Methods. [Citation Graph (, )][DBLP]


  78. A Delay-efficient Radiation-hard Digital Design Approach Using CWSP Elements. [Citation Graph (, )][DBLP]


  79. Towards fault tolerant parallel prefix adders in nanoelectronic systems. [Citation Graph (, )][DBLP]


  80. A Novel Low Overhead Fault Tolerant Kogge-Stone Adder Using Adaptive Clocking. [Citation Graph (, )][DBLP]


  81. Embedded Tutorial - Software for Wireless Networked Embedded Systems. [Citation Graph (, )][DBLP]


  82. Fine-Grained Supply Gating Through Hypergraph Partitioning and Shannon Decomposition for Active Power Reduction. [Citation Graph (, )][DBLP]


  83. A Scalable Algorithmic Framework for Row-Based Power-Gating. [Citation Graph (, )][DBLP]


  84. Coarse-Grain MTCMOS Sleep Transistor Sizing Using Delay Budgeting. [Citation Graph (, )][DBLP]


  85. Physical Architectures of Automotive Systems. [Citation Graph (, )][DBLP]


  86. A Mutation Model for the SystemC TLM 2.0 Communication Interfaces. [Citation Graph (, )][DBLP]


  87. Efficient Design Validation Based on Cultural Algorithms. [Citation Graph (, )][DBLP]


  88. Algorithms for Maximum Satisfiability using Unsatisfiable Cores. [Citation Graph (, )][DBLP]


  89. In-band Cross-Trigger Event Transmission for Transaction-Based Debug. [Citation Graph (, )][DBLP]


  90. Efficient Representation and Analysis of Power Grids. [Citation Graph (, )][DBLP]


  91. High-Frequency Mutual Impedance Extraction of VLSI Interconnects In the Presence of a Multi-layer Conducting Substrate. [Citation Graph (, )][DBLP]


  92. ETBR: Extended Truncated Balanced Realization Method for On-Chip Power Grid Network Analysis. [Citation Graph (, )][DBLP]


  93. Bandwidth-Centric Optimisation for Area-Constrained Links with Crosstalk Avoidance Methods. [Citation Graph (, )][DBLP]


  94. Optimizing Near-ML MIMO Detector for SDR Baseband on Parallel Programmable Architectures. [Citation Graph (, )][DBLP]


  95. Vectorization of Reed Solomon Decoding and Mapping on the EVP. [Citation Graph (, )][DBLP]


  96. A Case Study in Reliability-Aware Design: A Resilient LDPC Code Decoder. [Citation Graph (, )][DBLP]


  97. Low Power Illinois Scan Architecture for Simultaneous Power and Test Data Volume Reduction. [Citation Graph (, )][DBLP]


  98. Scan Chain Organization for Embedded Diagnosis. [Citation Graph (, )][DBLP]


  99. State Skip LFSRs: Bridging the Gap between Test Data Compression and Test Set Embedding for IP Cores. [Citation Graph (, )][DBLP]


  100. Automated Testability Enhancements for Logic Brick Libraries. [Citation Graph (, )][DBLP]


  101. A Game-Theoretic Approach to Real-Time System Testing. [Citation Graph (, )][DBLP]


  102. Modeling Event Stream Hierarchies with Hierarchical Event Models. [Citation Graph (, )][DBLP]


  103. Semantics for Model-Based Validation of Continuous/Discrete Systems. [Citation Graph (, )][DBLP]


  104. Using UML as Front-end for Heterogeneous Software Code Generation Strategies. [Citation Graph (, )][DBLP]


  105. Panel Session - Caution Ahead: The Road to Design and Manufacturing at 32 and 22 nm. [Citation Graph (, )][DBLP]


  106. Fault Clustering in deep-submicron CMOS Processes. [Citation Graph (, )][DBLP]


  107. Energy Efficient and High Speed On-Chip Ternary Bus. [Citation Graph (, )][DBLP]


  108. Task Scheduling with Configuration Prefetching and Anti-Fragmentation techniques on Dynamically Reconfigurable Systems. [Citation Graph (, )][DBLP]


  109. Fast Analog Circuit Synthesis Using Sensitivity Based Near Neighbor Searches. [Citation Graph (, )][DBLP]


  110. Spatial Correlation Extraction via Random Field Simulation and Production Chip Performance Regression. [Citation Graph (, )][DBLP]


  111. A methodology for improving software design lifecycle in embedded control systems. [Citation Graph (, )][DBLP]


  112. Finding the Worst Voltage Violation in Multi-Domain Clock Gated Power Network. [Citation Graph (, )][DBLP]


  113. A System Architecture for Reconfigurable Trusted Platforms. [Citation Graph (, )][DBLP]


  114. Automatic Generation of Complex Properties for Hardware Designs. [Citation Graph (, )][DBLP]


  115. Software Components for Reliable Automotive Systems. [Citation Graph (, )][DBLP]


  116. Model-Based-Design Is Nice But... [Citation Graph (, )][DBLP]


  117. A Simulation Methodology for Worst-Case Response Time Estimation of Distributed Real-Time Systems. [Citation Graph (, )][DBLP]


  118. Signal Probability Based Statistical Timing Analysis. [Citation Graph (, )][DBLP]


  119. A Current Source Model for CMOS Logic Cells Considering Multiple Input Switching and Stack Effect. [Citation Graph (, )][DBLP]


  120. Current source based standard cell model for accurate signal integrity and timing analysis. [Citation Graph (, )][DBLP]


  121. An Efficient Method for Chip-Level Statistical Capacitance Extraction Considering Process Variations with Spatial Correlation. [Citation Graph (, )][DBLP]


  122. SPARE - a Scalable algorithm for passive, structure preserving, Parameter-Aware model order REduction. [Citation Graph (, )][DBLP]


  123. Transistor-Specific Delay Modeling for SSTA. [Citation Graph (, )][DBLP]


  124. Generic Multi-Phase Software-Pipelined Partial-FFT on Instruction-Level-Parallel Architectures and SDR Baseband Applications. [Citation Graph (, )][DBLP]


  125. A Novel Recursive Algorithm for Bit-Efficient Realization of Arbitrary Length Inverse Modified Cosine Transforms. [Citation Graph (, )][DBLP]


  126. Definition and SIMD Implementation of a Multi-Processing Architecture Approach on FPGA. [Citation Graph (, )][DBLP]


  127. On Modeling and Testing of Lithography Related Open Faults in Nano-CMOS Circuits. [Citation Graph (, )][DBLP]


  128. Optimal Margin Computation for At-Speed Test. [Citation Graph (, )][DBLP]


  129. Resistive Bridging Fault Simulation of Industrial Circuits. [Citation Graph (, )][DBLP]


  130. Physically-Aware N-Detect Test Pattern Selection. [Citation Graph (, )][DBLP]


  131. Computation of Buffer Capacities for Throughput Constrained and Data Dependent Inter-Task Communication. [Citation Graph (, )][DBLP]


  132. Constraint Refinement for Online Verifiable Cross-Layer System Adaptation. [Citation Graph (, )][DBLP]


  133. Adaptive Scheduling and Voltage Scaling for Multiprocessor Real-time Applications with Non-deterministic Workload. [Citation Graph (, )][DBLP]


  134. Embedded Tutorial - ARTEMIS and ENIAC Joint Undertakings: A New Approach to Conduct Research in Europe. [Citation Graph (, )][DBLP]


  135. Methods, Tools and Standards for the Analysis, Evaluation and Design of Modern Automotive Architectures. [Citation Graph (, )][DBLP]


  136. Random Stimulus Generation using Entropy and XOR Constraints. [Citation Graph (, )][DBLP]


  137. MCjammer: Adaptive Verification for Multi-core Designs. [Citation Graph (, )][DBLP]


  138. Efficient Implementation of Native Software Simulation for MPSoC. [Citation Graph (, )][DBLP]


  139. Simulation-Directed Invariant Mining for Software Verification. [Citation Graph (, )][DBLP]


  140. Comparison of Opamp-Based and Comparator-Based Delta-Sigma Modulation. [Citation Graph (, )][DBLP]


  141. A Novel Technique for Improving Temperature Independency of Ring-ADC. [Citation Graph (, )][DBLP]


  142. An Analog On-Chip Adaptive Body Bias Calibration for Reducing Mismatches in Transistor Pairs. [Citation Graph (, )][DBLP]


  143. Integrated approach to energy harvester mixed technology modelling and performance optimisation. [Citation Graph (, )][DBLP]


  144. A scalable low-power digital communication network architecture and an automated design path for controlling the analog/RF part of SDR transceivers. [Citation Graph (, )][DBLP]


  145. A Coarse-Grained Array based Baseband Processor for 100Mbps+ Software Defined Radio. [Citation Graph (, )][DBLP]


  146. Scenario-Based Fixed-point Data Format Refinement to Enable Energy-scalable Software Defined Radios. [Citation Graph (, )][DBLP]


  147. Test Strategies for Low Power Devices. [Citation Graph (, )][DBLP]


  148. Thermal Balancing Policy for Streaming Computing on Multiprocessor Architectures. [Citation Graph (, )][DBLP]


  149. A Practical Approach for Reconciling High and Predictable Performance in Non-Regular Parallel Programs. [Citation Graph (, )][DBLP]


  150. Exact and Approximate Task Assignment Algorithms for Pipelined Software Synthesis. [Citation Graph (, )][DBLP]


  151. Run-time System for an Extensible Embedded Processor with Dynamic Instruction Set. [Citation Graph (, )][DBLP]


  152. Harnessing Horizontal Parallelism and Vertical Instruction Packing of Programs to Improve System Overall Efficiency. [Citation Graph (, )][DBLP]


  153. Instruction Set Extension Exploration in Multiple-Issue Architecture. [Citation Graph (, )][DBLP]


  154. Instruction Re-encoding Facilitating Dense Embedded Code. [Citation Graph (, )][DBLP]


  155. Test Instrumentation for a Laser Scanning Localization Technique for Analysis of High Speed DRAM devices. [Citation Graph (, )][DBLP]


  156. A Mapping Framework for Guided Design Space Exploration of Heterogeneous MP-SoCs. [Citation Graph (, )][DBLP]


  157. Impact of Leakage Current on Data Retention of RF-powered Devices During Amplitude-Modulation-based Communication. [Citation Graph (, )][DBLP]


  158. Accuracy-Adaptive Simulation of Transaction Level Models. [Citation Graph (, )][DBLP]


  159. Zero-Efficient Buffer Design for Reliable Network-on-Chip in Tiled Chip-Multi-Processor. [Citation Graph (, )][DBLP]


  160. Wire Sizing Alternative - An Uniform Dual-rail Routing Architecture. [Citation Graph (, )][DBLP]


  161. Structural Synthesis of Four-Quadrant Multiplier Based on Hierarchical Topology. [Citation Graph (, )][DBLP]


  162. A Virtual Prototype for Bluetooth over Ultra Wide Band System Level Design. [Citation Graph (, )][DBLP]


  163. Re-Examining the Use of Network-on-Chip as Test Access Mechanism. [Citation Graph (, )][DBLP]


  164. Panel Session - The Future Car: Technology, Methods and Tools. [Citation Graph (, )][DBLP]


  165. Improving Constant-Coefficient Multiplier Verification by Partial Product Identification. [Citation Graph (, )][DBLP]


  166. Improved Visibility in One-to-Many Trace Concretization. [Citation Graph (, )][DBLP]


  167. Efficient Symbolic Simulation of Low Level Software. [Citation Graph (, )][DBLP]


  168. Completeness in SMT-based BMC for Software Programs. [Citation Graph (, )][DBLP]


  169. Novel Pin Assignment Algorithms for Components with Very High Pin Counts. [Citation Graph (, )][DBLP]


  170. A Generic Standard Cell Design Methodology for Differential Circuit Styles. [Citation Graph (, )][DBLP]


  171. Layout Level Timing Optimization by Leveraging Active Area Dependent Mobility of Strained-Silicon Devices. [Citation Graph (, )][DBLP]


  172. Exploiting Correlation Kernels for Efficient Handling of Intra-Die Spatial Correlation, with Application to Statistical Timing. [Citation Graph (, )][DBLP]


  173. A Triple-Mode Reconfigurable Sigma-Delta Modulator for Multi-Standard Wireless Applications. [Citation Graph (, )][DBLP]


  174. Low-Noise Sigma-Delta Capacitance-to-Digital Converter for Sub-pF Capacitive Sensors with Integrated Dielectric Loss Measurement. [Citation Graph (, )][DBLP]


  175. Calibration of Integrated CMOS Hall Sensors Using Coil-on-Chip in ATE Environment. [Citation Graph (, )][DBLP]


  176. A Programmable and Low-EMI Integrated Half-Bridge Driver in BCD Technology. [Citation Graph (, )][DBLP]


  177. CASP: Concurrent Autonomous Chip Self-Test Using Stored Test Patterns. [Citation Graph (, )][DBLP]


  178. Defect Tolerance in Homogeneous Manycore Processors Using Core-Level Redundancy with Unified Topology. [Citation Graph (, )][DBLP]


  179. A low-cost concurrent error detection technique for processor control logic. [Citation Graph (, )][DBLP]


  180. Approximate logic circuits for low overhead, non-intrusive concurrent error detection. [Citation Graph (, )][DBLP]


  181. Logical Reliability of Interacting Real-Time Tasks. [Citation Graph (, )][DBLP]


  182. Scheduling of Fault-Tolerant Embedded Systems with Soft and Hard Timing Constraints. [Citation Graph (, )][DBLP]


  183. Tool Support for Incremental Failure Mode and Effects Analysis of Component-Based Systems. [Citation Graph (, )][DBLP]


  184. Compositional design of isochronous systems. [Citation Graph (, )][DBLP]


  185. Quantitative Productivity Measurement in IC Design. [Citation Graph (, )][DBLP]


  186. Qalitative and Quantitative Analysis of IC Designs. [Citation Graph (, )][DBLP]


  187. Determining the Technical Complexity of Integrated Circuits. [Citation Graph (, )][DBLP]


  188. Capturing and Analyzing IC Design Productivity Metrics. [Citation Graph (, )][DBLP]


  189. Application of Workflow Petri Nets to Modeling of Formal Verification Processes in Design Flow of Digital Integrated Circuits. [Citation Graph (, )][DBLP]


  190. Optimization of Design Flows for Multi-Core x86 Microprocessors in 45 and 32nm Technologies under Productivity Considerations. [Citation Graph (, )][DBLP]


  191. Implications of Technology Trends on System Dependability. [Citation Graph (, )][DBLP]


  192. Globally Optimized Robust Systems to Overcome Scaled CMOS Reliability Challenges. [Citation Graph (, )][DBLP]


  193. Software Protection Mechanisms for Dependable Systems. [Citation Graph (, )][DBLP]


  194. Subsystem Exchange in a Concurrent Design Process Environment. [Citation Graph (, )][DBLP]


  195. Cooperative Safety: a Combination of Multiple Technologies. [Citation Graph (, )][DBLP]


  196. System Performance Optimization Methodology for Infineon's 32-Bit Automotive Microcontroller Architecture. [Citation Graph (, )][DBLP]


  197. Process Variation Tolerant Pipeline Design Through a Placement-Aware Multiple Voltage Island Design Style. [Citation Graph (, )][DBLP]


  198. Optimal MTCMOS Reactivation Under Power Supply Noise and Performance Constraints. [Citation Graph (, )][DBLP]


  199. A Single-supply True Voltage Level Shifter. [Citation Graph (, )][DBLP]


  200. Clock Distribution Scheme using Coplanar Transmission Lines. [Citation Graph (, )][DBLP]


  201. Compositional, dynamic cache management for embedded chip multiprocessors. [Citation Graph (, )][DBLP]


  202. Comparison of memory write policies for NoC based Multicore Cache Coherent Systems. [Citation Graph (, )][DBLP]


  203. Serialized Asynchronous Links for NoC. [Citation Graph (, )][DBLP]


  204. Design Guidelines for Metallic-Carbon-Nanotube-Tolerant Digital Logic Circuits. [Citation Graph (, )][DBLP]


  205. Quantified Synthesis of Reversible Logic. [Citation Graph (, )][DBLP]


  206. Adaptive Simulation for Single-Electron Devices. [Citation Graph (, )][DBLP]


  207. OS-Based Sensor Node Platform and Energy Estimation Model for Health-Care Wireless Sensor Networks. [Citation Graph (, )][DBLP]


  208. Improvements in Polynomial-Time Feasibility Testing for EDF. [Citation Graph (, )][DBLP]


  209. A Dual-Priority Real-Time Multiprocessor System on FPGA for Automotive Applications. [Citation Graph (, )][DBLP]


  210. An application-based EDF scheduler for OSEK/VDX. [Citation Graph (, )][DBLP]


  211. Time Properties of the BuST Protocol under the NPA Budget Allocation Scheme. [Citation Graph (, )][DBLP]


  212. Simultaneous FU and Register Binding Based on Network Flow Method. [Citation Graph (, )][DBLP]


  213. A Variation Aware High Level Synthesis Framework. [Citation Graph (, )][DBLP]


  214. EPIC: Ending Piracy of Integrated Circuits. [Citation Graph (, )][DBLP]


  215. VLSI implementation of SISO arithmetic decoders for joint source channel coding. [Citation Graph (, )][DBLP]


  216. Error Detection/Correction in DNA Algorithmic Self-Assembly. [Citation Graph (, )][DBLP]


  217. Temperature-Aware Voltage Selection for Energy Optimization. [Citation Graph (, )][DBLP]


  218. A Fast Approximation Algorithm for MIN-ONE SAT. [Citation Graph (, )][DBLP]


  219. Deep Submicron Interconnect Timing Model with Quadratic Random Variable Analysis. [Citation Graph (, )][DBLP]


  220. An efficient algorithm for free resources management on the FPGA. [Citation Graph (, )][DBLP]


  221. Performance-Constrained Different Cell Count Minimization for Continuously-Sized Circuits. [Citation Graph (, )][DBLP]


  222. Test Scheduling for Wafer-Level Test-During-Burn-In of Core-Based SoCs. [Citation Graph (, )][DBLP]


  223. CARbridge, Reduction of System Complexity by Standardisation of the System-Basis-Chips for Automotive Applications. [Citation Graph (, )][DBLP]


  224. Specification and Design Considerations for Reliable Embedded Systems. [Citation Graph (, )][DBLP]


  225. Synthesis of Fault-Tolerant Embedded Systems. [Citation Graph (, )][DBLP]


  226. Reliable Services in an Imperfect World. [Citation Graph (, )][DBLP]


  227. Video Processing Requirements on SoC Infrastructures. [Citation Graph (, )][DBLP]


  228. Memory Technology for Extended Large-Scale Integration in Future Electronics Applications. [Citation Graph (, )][DBLP]


  229. Memory-aware NoC Exploration and Design. [Citation Graph (, )][DBLP]


  230. Incremental Criticality and Yield Gradients. [Citation Graph (, )][DBLP]


  231. Latch Modeling for Statistical Timing Analysis. [Citation Graph (, )][DBLP]


  232. Conditional Partial Order Graphs and Dynamically Reconfigurable Control Synthesis. [Citation Graph (, )][DBLP]


  233. Efficient Software Architecture for IPSec Acceleration Using a Programmable Security Processor. [Citation Graph (, )][DBLP]


  234. Operating System Controlled Processor-Memory Bus Encryption. [Citation Graph (, )][DBLP]


  235. An Efficient FPGA Implementation of Principle Component Analysis based Network Intrusion Detection System. [Citation Graph (, )][DBLP]


  236. A Bridging Fault Model Where Undetectable Faults Imply Logic Redundancy. [Citation Graph (, )][DBLP]


  237. Layout-Aware, IR-Drop Tolerant Transition Fault Pattern Generation. [Citation Graph (, )][DBLP]


  238. Multi-Vector Tests: A Path to Perfect Error-Rate Testing. [Citation Graph (, )][DBLP]


  239. iFill: An Impact-Oriented X-Filling Method for Shift- and Capture-Power Reduction in At-Speed Scan-Based Testing. [Citation Graph (, )][DBLP]


  240. Hiding Cache Miss Penalty Using Priority-based Execution for Embedded Processors. [Citation Graph (, )][DBLP]


  241. Instruction Cache Energy Saving Through Compiler Way-Placement. [Citation Graph (, )][DBLP]


  242. Effective Loop Partitioning and Scheduling under Memory and Register Dual Constraints. [Citation Graph (, )][DBLP]


  243. Transparent Reconfigurable Acceleration for Heterogeneous Embedded Applications. [Citation Graph (, )][DBLP]


  244. Automatic Selection of Application-Specific Reconfigurable Processor Extensions. [Citation Graph (, )][DBLP]


  245. An Optimized Message Passing Framework for Parallel Implementation of Signal Processing Applications. [Citation Graph (, )][DBLP]


  246. Dependability for high-tech systems: an industry-as-laboratory approach. [Citation Graph (, )][DBLP]


  247. User-Aware Dynamic Task Allocation in Networks-on-Chip. [Citation Graph (, )][DBLP]


  248. Minimizing Virtual Channel Buffer for Routers in On-chip Communication Architectures. [Citation Graph (, )][DBLP]


  249. An Open-Loop Flow Control Scheme Based on the Accurate Global Information of On-Chip Communication. [Citation Graph (, )][DBLP]


  250. Variable Latency Speculative Addition: A New Paradigm for Arithmetic Circuit Design. [Citation Graph (, )][DBLP]


  251. Improving Synthesis of Compressor Trees on FPGAs via Integer Linear Programming. [Citation Graph (, )][DBLP]


  252. An adaptable FPGA-based System for Regular Expression Matching. [Citation Graph (, )][DBLP]


  253. Comparison of Boolean Satisfiability Encodings on FPGA Detailed Routing Problems. [Citation Graph (, )][DBLP]


  254. Defeating classical Hardware Countermeasures: a new processing for Side Channel Analysis. [Citation Graph (, )][DBLP]


  255. Power Balanced Gates Insensitive to Routing Capacitance Mismatch. [Citation Graph (, )][DBLP]


  256. On Analysis and Synthesis of (n, k)-Non-Linear Feedback Shift Registers. [Citation Graph (, )][DBLP]


  257. FPGA Design for Algebraic Tori-Based Public-Key Cryptography. [Citation Graph (, )][DBLP]


  258. Automated Trace Signals Identification and State Restoration for Improving Observability in Post-Silicon Validation. [Citation Graph (, )][DBLP]


  259. Functional Self-Testing for Bus-Based Symmetric Multiprocessors. [Citation Graph (, )][DBLP]


  260. Theoretical and Practical Aspects of IDDQ Settling-Impact on Measurement Timing and Quality. [Citation Graph (, )][DBLP]


  261. Advanced Analog Filters for Telecommunications. [Citation Graph (, )][DBLP]


  262. Emerging Yield and Reliability Challenges in Nanometer CMOS Technologies. [Citation Graph (, )][DBLP]


  263. Novel Front-End Circuit Architectures for Integrated Bio-Electronic Interfaces. [Citation Graph (, )][DBLP]


  264. High-level Modelling and Exploration of Coarse-grained Re-configurable Architectures. [Citation Graph (, )][DBLP]


  265. Scalable Architecture for on-Chip Neural Network Training using Swarm Intelligence. [Citation Graph (, )][DBLP]


  266. Intelligent Merging Online Task Placement Algorithm for Partial Reconfigurable Systems. [Citation Graph (, )][DBLP]


  267. Design of a HW/SW Communication Infrastructure for a Heterogeneous Reconfigurable Processor. [Citation Graph (, )][DBLP]


  268. Automated Dynamic Throughput-constrained Structural-level Pipelining in Streaming Applications. [Citation Graph (, )][DBLP]


  269. Towards Trojan-Free Trusted ICs: Problem Analysis and Detection Scheme. [Citation Graph (, )][DBLP]


  270. Wrapper and TAM Co-Optimization for Reuse of SoC Functional Interconnects. [Citation Graph (, )][DBLP]


  271. De Bruijn Graph as a Low Latency Scalable Architecture for Energy Efficient Massive NoCs. [Citation Graph (, )][DBLP]


  272. Adaptive Filesystem Compression for Embedded Systems. [Citation Graph (, )][DBLP]


  273. Partially Redundant Logic Detection Using Symbolic Equivalence Checking in Reversible and Irreversible Logic Circuits. [Citation Graph (, )][DBLP]


  274. TinyTimber, Reactive Objects in C for Real-Time Embedded Systems. [Citation Graph (, )][DBLP]


  275. Dynamic Task Allocation Strategies in MPSoC for Soft Real-time Applications. [Citation Graph (, )][DBLP]


  276. Mixed-Signal Design Space Exploration of Time-Interleaved A/D Converters for Ultra-Wide Band Applications. [Citation Graph (, )][DBLP]


  277. Dependable Embedded Systems Special Day Panel: Issues and Challenges in Dependable Embedded Systems. [Citation Graph (, )][DBLP]


  278. Multicast Parallel Pipeline Router Architecture for Network-on-Chip. [Citation Graph (, )][DBLP]


  279. Variation tolerant NoC design by means of self-calibrating links. [Citation Graph (, )][DBLP]


  280. BARP-A Dynamic Routing Protocol for Balanced Distribution of Traffic in NoCs. [Citation Graph (, )][DBLP]


  281. Developing Mesochronous Synchronizers to Enable 3D NoCs. [Citation Graph (, )][DBLP]


  282. Memory Organization with Multi-Pattern Parallel Accesses. [Citation Graph (, )][DBLP]


  283. CATCH: A Mechanism for Dynamically Detecting Cache-Content-Duplication and its Application to Instruction Caches. [Citation Graph (, )][DBLP]


  284. Magellan: A Search and Machine Learning-based Framework for Fast Multi-core Design Space Exploration and Optimization. [Citation Graph (, )][DBLP]


  285. Process Variation Aware Issue Queue Design. [Citation Graph (, )][DBLP]


  286. Implementation of Parallel LFSR-based Applications on an Adaptive DSP featuring a Pipelined Configurable Gate Array. [Citation Graph (, )][DBLP]


  287. GMDS: Hardware implementation of novel real output queuing architecture. [Citation Graph (, )][DBLP]


  288. Front End Device for Content Networking. [Citation Graph (, )][DBLP]


  289. Power Aware Reconfigurable Multiprocessor for Elliptic Curve Cryptography. [Citation Graph (, )][DBLP]


  290. Digital bit stream jitter testing using jitter expansion. [Citation Graph (, )][DBLP]


  291. A Same/Different Fault Dictionary: An Extended Pass/Fail Fault Dictionary with Improved Diagnostic Resolution. [Citation Graph (, )][DBLP]


  292. A Design-for-Diagnosis Technique for SRAM Write Drivers. [Citation Graph (, )][DBLP]


  293. Variable Delay of Multi-Gigahertz Digital Signals for Deskew and Jitter-Injection Test Applications. [Citation Graph (, )][DBLP]


  294. Retargetable Code Optimization for Predicated Execution. [Citation Graph (, )][DBLP]


  295. Programming Shared Memory Multiprocessors with Deterministic Message-Passing Concurrency: Compiling SHIM to Pthreads. [Citation Graph (, )][DBLP]


  296. Modularity vs. Reusability: Code Generation from Synchronous Block Diagrams. [Citation Graph (, )][DBLP]


  297. ezRealtime: A Domain-Specific Modeling Tool for Embedded Hard Real-Time Software Synthesis. [Citation Graph (, )][DBLP]


  298. HOT TOPIC - 3D Integration or How to Scale in the 21st Century. [Citation Graph (, )][DBLP]

NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002