Conferences in DBLP
RATAN: A tool for rate analysis and rate constraint debugging for embedded systems. [Citation Graph (, )][DBLP ] Efficient utilization of scratch-pad memory in embedded processor applications. [Citation Graph (, )][DBLP ] Interface timing verification with delay correlation using constraint logic programming. [Citation Graph (, )][DBLP ] Sequential circuit test generation using dynamic state traversal. [Citation Graph (, )][DBLP ] MOSAIC: a multiple-strategy oriented sequential ATPG for integrated circuits. [Citation Graph (, )][DBLP ] New static compaction techniques of test sequences for sequential circuits. [Citation Graph (, )][DBLP ] A methodology for designing continuous-time sigma-delta modulators. [Citation Graph (, )][DBLP ] A CMOS low-voltage, high-gain op-amp. [Citation Graph (, )][DBLP ] High-level synthesis of analog sensor interface front-ends. [Citation Graph (, )][DBLP ] Structural BIST insertion using behavioral test analysis. [Citation Graph (, )][DBLP ] On the generation of pseudo-deterministic two-patterns test sequence with LFSRs. [Citation Graph (, )][DBLP ] Cellular automata for generating deterministic test sequences. [Citation Graph (, )][DBLP ] Fast controllers for data dominated applications. [Citation Graph (, )][DBLP ] Random benchmark circuits with controlled attributes. [Citation Graph (, )][DBLP ] Technology mapping of speed-independent circuits based on combinational decomposition and resynthesis. [Citation Graph (, )][DBLP ] Generation of the HDL-A-model of a micromembrane from its finite-element-description. [Citation Graph (, )][DBLP ] Microsystem design using simulator coupling. [Citation Graph (, )][DBLP ] Modeling and simulation of electromechanical transducers in microsystems using an analog hardware description language. [Citation Graph (, )][DBLP ] Delay management for programmable video signal processors. [Citation Graph (, )][DBLP ] Hierarchical scheduling and allocation of multirate systems on heterogeneous multiprocessors. [Citation Graph (, )][DBLP ] Retargetable generation of code selectors from HDL processor models. [Citation Graph (, )][DBLP ] An RTL methodology to enable low overhead combinational testing. [Citation Graph (, )][DBLP ] A controller testability analysis and enhancement technique. [Citation Graph (, )][DBLP ] Analyzing testability from behavioral to RT level. [Citation Graph (, )][DBLP ] Fast and efficient construction of BDDs by reordering based synthesis. [Citation Graph (, )][DBLP ] Verification and synthesis of counters based on symbolic techniques. [Citation Graph (, )][DBLP ] Using MTBDDs for discrete timed symbolic model checking. [Citation Graph (, )][DBLP ] Analysis of 3D conjugate heat transfers in electronics. [Citation Graph (, )][DBLP ] Smart sensor system application: an integrated compass. [Citation Graph (, )][DBLP ] Automatic transfer of parametric FEM models into CAD-layout formats for top-down design of microsystems. [Citation Graph (, )][DBLP ] Highly scalable parallel parametrizable architecture of the motion estimator. [Citation Graph (, )][DBLP ] Design and implementation of a coprocessor for cryptography applications. [Citation Graph (, )][DBLP ] On the way to the 2.5 Gbits/s ATM network ATM multiplexer demultiplexer ASIC. [Citation Graph (, )][DBLP ] Solving graph optimization problems with ZBDDs. [Citation Graph (, )][DBLP ] Minimizing ROBDD sizes of incompletely specified Boolean functionsby exploiting strong symmetries. [Citation Graph (, )][DBLP ] Connection error location and correction in combinational circuits. [Citation Graph (, )][DBLP ] Shaping a VLSI wire to minimize Elmore delay. [Citation Graph (, )][DBLP ] Inductance analysis of on-chip interconnects [deep submicron CMOS]. [Citation Graph (, )][DBLP ] Cartesian multipole based numerical integration for 3D capacitance extraction. [Citation Graph (, )][DBLP ] CCII+ current conveyor based BIC monitor for IDDQ testing of complex CMOS circuits. [Citation Graph (, )][DBLP ] Deep sub-micron IDDQ testing: issues and solutions. [Citation Graph (, )][DBLP ] A production-oriented measurement method for fast and exhaustive Iddq tests. [Citation Graph (, )][DBLP ] Library mapping for memories. [Citation Graph (, )][DBLP ] Architectural exploration and optimization for counter based hardware address generation. [Citation Graph (, )][DBLP ] RTL synthesis with physical and controller information. [Citation Graph (, )][DBLP ] Two-way partitioning based on direction vector [layout design]. [Citation Graph (, )][DBLP ] Multi-layer chip-level global routing using an efficient graph-based Steiner tree heuristic. [Citation Graph (, )][DBLP ] A gridless multi-layer router for standard cell circuits using CTM cells. [Citation Graph (, )][DBLP ] A programmable boundary scan technique for board-level, parallel functional duplex march testing of word-oriented multiport static RAMs. [Citation Graph (, )][DBLP ] Fault-secure shifter design: results and implementations. [Citation Graph (, )][DBLP ] High-speed C-testable systolic array design for Galois-field inversion. [Citation Graph (, )][DBLP ] Efficient and accurate testing of analog-to-digital converters using oscillation-test method. [Citation Graph (, )][DBLP ] Built-in self-test methodology for A/D converters. [Citation Graph (, )][DBLP ] Reconfigurable data converter as a building block for mixed-signal test. [Citation Graph (, )][DBLP ] VHDL extensions for complex transmission line simulation. [Citation Graph (, )][DBLP ] Acceleration of behavioral simulation on simulation specific machines. [Citation Graph (, )][DBLP ] Exploiting temporal independence in distributed preemptive circuit simulation. [Citation Graph (, )][DBLP ] Analogue layout generation by World Wide Web server-based agents. [Citation Graph (, )][DBLP ] A performance-driven placement algorithm with simultaneous Place&Route optimization for analog ICs. [Citation Graph (, )][DBLP ] An algorithm for numerical reference generation in symbolic analysis of large analog circuits. [Citation Graph (, )][DBLP ] Adaptive least mean square behavioral power modeling. [Citation Graph (, )][DBLP ] Fast power loss calculation for digital static CMOS circuits. [Citation Graph (, )][DBLP ] Monte-Carlo approach for power estimation in sequential circuits. [Citation Graph (, )][DBLP ] Hybrid symbolic-explicit techniques for the graph coloring problem. [Citation Graph (, )][DBLP ] A constructive approach towards correctness of synthesis-application within retiming. [Citation Graph (, )][DBLP ] A symbolic core approach to the formal verification of integrated mixed-mode applications. [Citation Graph (, )][DBLP ] A novel methodology for designing TSC networks based on the parity bit code. [Citation Graph (, )][DBLP ] Testing scheme for IC's clocks. [Citation Graph (, )][DBLP ] A totally self-checking 1-out-of-3 code error indicator. [Citation Graph (, )][DBLP ] Cone-based clustering heuristic for list-scheduling algorithms. [Citation Graph (, )][DBLP ] Register synthesis for speculative computation. [Citation Graph (, )][DBLP ] Multidimensional periodic scheduling: a solution approach. [Citation Graph (, )][DBLP ] Multi-thread graph: a system model for real-time embedded software synthesis. [Citation Graph (, )][DBLP ] PCC: a modeling technique for mixed control/data flow systems. [Citation Graph (, )][DBLP ] Procedure cloning: a transformation for improved system-level functional partitioning. [Citation Graph (, )][DBLP ] A fault diagnosis methodology for the UltraSPARCTM -I microprocessor. [Citation Graph (, )][DBLP ] Improved diagnosis of realistic interconnect shorts. [Citation Graph (, )][DBLP ] On improving genetic optimization based test generation. [Citation Graph (, )][DBLP ] Symbolic synthesis of clock-gating logic for power optimization of control-oriented synchronous networks. [Citation Graph (, )][DBLP ] Low power FSM design using Huffman-style encoding. [Citation Graph (, )][DBLP ] Improving the accuracy of support-set finding method for power estimation of combinational circuits. [Citation Graph (, )][DBLP ] Practical concurrent ASIC and system design and verification. [Citation Graph (, )][DBLP ] A methodology for hardware architecture trade-off at different levels of abstraction. [Citation Graph (, )][DBLP ] Synthesis of multi-rate and variable rate circuits for high speed telecommunications applications. [Citation Graph (, )][DBLP ] Testability of 2-level AND/EXOR circuits. [Citation Graph (, )][DBLP ] On the use of reset to increase the testability of interconnected finite-state machines. [Citation Graph (, )][DBLP ] A new approach to build a low-level malicious fault list starting from high-level description and alternative graphs. [Citation Graph (, )][DBLP ] On-chip analog output response compaction. [Citation Graph (, )][DBLP ] A new quality estimation methodology for mixed-signal and analogue ICs. [Citation Graph (, )][DBLP ] Compact structural test generation for analog macros. [Citation Graph (, )][DBLP ] Accurate high level datapath power estimation. [Citation Graph (, )][DBLP ] Maximizing the weighted switching activity in combinational CMOS circuits under the variable delay model. [Citation Graph (, )][DBLP ] Internal power modelling and minimization in CMOS inverters. [Citation Graph (, )][DBLP ] A new field programmable system-on-a-chip for mixed signal integration. [Citation Graph (, )][DBLP ] PROPHID: a data-driven multi-processor architecture for high-performance DSP. [Citation Graph (, )][DBLP ] ReCode: the design and re-design of the instruction codes for embedded instruction-set processors. [Citation Graph (, )][DBLP ] A real-time smart sensor system for visual motion estimation. [Citation Graph (, )][DBLP ] Full custom chip set for high speed serial communications up to 2.48 Gbit/s. [Citation Graph (, )][DBLP ] An asynchronous architecture for digital signal processors. [Citation Graph (, )][DBLP ] Test synthesis for DC test of switched-capacitors circuits. [Citation Graph (, )][DBLP ] SISSSI-A tool for dynamic electro-thermal simulation of analog VLSI cells. [Citation Graph (, )][DBLP ] Design of oscillation-based test structures for active RC filters. [Citation Graph (, )][DBLP ] Using constraint logic programming in memory synthesis for general purpose computers. [Citation Graph (, )][DBLP ] Optimal scheduling for fast systolic array implementations. [Citation Graph (, )][DBLP ] Scheduling using mixed arithmetic: an ILP formulation. [Citation Graph (, )][DBLP ] Performance verification using partial evaluation and interval analysis. [Citation Graph (, )][DBLP ] Design and verification of the sequential systems automata using temporal logic specifications. [Citation Graph (, )][DBLP ] Application independent module generation in analog layouts. [Citation Graph (, )][DBLP ] A scheme for multiple on-chip signature checking for embedded SRAMs. [Citation Graph (, )][DBLP ] Design of partially parallel scan chain. [Citation Graph (, )][DBLP ] March LA: a test for linked memory faults. [Citation Graph (, )][DBLP ] The input pattern fault model and its application. [Citation Graph (, )][DBLP ] A monolithic off-chip IDDQ monitor. [Citation Graph (, )][DBLP ] Extension of the boundary-scan architecture and new idea of BIST for more effective testing and self-testing of interconnections. [Citation Graph (, )][DBLP ]