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Conferences in DBLP

Design, Automation, and Test in Europe (date)
1997 (conf/date/1997)


  1. RATAN: A tool for rate analysis and rate constraint debugging for embedded systems. [Citation Graph (, )][DBLP]


  2. Efficient utilization of scratch-pad memory in embedded processor applications. [Citation Graph (, )][DBLP]


  3. Interface timing verification with delay correlation using constraint logic programming. [Citation Graph (, )][DBLP]


  4. Sequential circuit test generation using dynamic state traversal. [Citation Graph (, )][DBLP]


  5. MOSAIC: a multiple-strategy oriented sequential ATPG for integrated circuits. [Citation Graph (, )][DBLP]


  6. New static compaction techniques of test sequences for sequential circuits. [Citation Graph (, )][DBLP]


  7. A methodology for designing continuous-time sigma-delta modulators. [Citation Graph (, )][DBLP]


  8. A CMOS low-voltage, high-gain op-amp. [Citation Graph (, )][DBLP]


  9. High-level synthesis of analog sensor interface front-ends. [Citation Graph (, )][DBLP]


  10. Structural BIST insertion using behavioral test analysis. [Citation Graph (, )][DBLP]


  11. On the generation of pseudo-deterministic two-patterns test sequence with LFSRs. [Citation Graph (, )][DBLP]


  12. Cellular automata for generating deterministic test sequences. [Citation Graph (, )][DBLP]


  13. Fast controllers for data dominated applications. [Citation Graph (, )][DBLP]


  14. Random benchmark circuits with controlled attributes. [Citation Graph (, )][DBLP]


  15. Technology mapping of speed-independent circuits based on combinational decomposition and resynthesis. [Citation Graph (, )][DBLP]


  16. Generation of the HDL-A-model of a micromembrane from its finite-element-description. [Citation Graph (, )][DBLP]


  17. Microsystem design using simulator coupling. [Citation Graph (, )][DBLP]


  18. Modeling and simulation of electromechanical transducers in microsystems using an analog hardware description language. [Citation Graph (, )][DBLP]


  19. Delay management for programmable video signal processors. [Citation Graph (, )][DBLP]


  20. Hierarchical scheduling and allocation of multirate systems on heterogeneous multiprocessors. [Citation Graph (, )][DBLP]


  21. Retargetable generation of code selectors from HDL processor models. [Citation Graph (, )][DBLP]


  22. An RTL methodology to enable low overhead combinational testing. [Citation Graph (, )][DBLP]


  23. A controller testability analysis and enhancement technique. [Citation Graph (, )][DBLP]


  24. Analyzing testability from behavioral to RT level. [Citation Graph (, )][DBLP]


  25. Fast and efficient construction of BDDs by reordering based synthesis. [Citation Graph (, )][DBLP]


  26. Verification and synthesis of counters based on symbolic techniques. [Citation Graph (, )][DBLP]


  27. Using MTBDDs for discrete timed symbolic model checking. [Citation Graph (, )][DBLP]


  28. Analysis of 3D conjugate heat transfers in electronics. [Citation Graph (, )][DBLP]


  29. Smart sensor system application: an integrated compass. [Citation Graph (, )][DBLP]


  30. Automatic transfer of parametric FEM models into CAD-layout formats for top-down design of microsystems. [Citation Graph (, )][DBLP]


  31. Highly scalable parallel parametrizable architecture of the motion estimator. [Citation Graph (, )][DBLP]


  32. Design and implementation of a coprocessor for cryptography applications. [Citation Graph (, )][DBLP]


  33. On the way to the 2.5 Gbits/s ATM network ATM multiplexer demultiplexer ASIC. [Citation Graph (, )][DBLP]


  34. Solving graph optimization problems with ZBDDs. [Citation Graph (, )][DBLP]


  35. Minimizing ROBDD sizes of incompletely specified Boolean functionsby exploiting strong symmetries. [Citation Graph (, )][DBLP]


  36. Connection error location and correction in combinational circuits. [Citation Graph (, )][DBLP]


  37. Shaping a VLSI wire to minimize Elmore delay. [Citation Graph (, )][DBLP]


  38. Inductance analysis of on-chip interconnects [deep submicron CMOS]. [Citation Graph (, )][DBLP]


  39. Cartesian multipole based numerical integration for 3D capacitance extraction. [Citation Graph (, )][DBLP]


  40. CCII+ current conveyor based BIC monitor for IDDQ testing of complex CMOS circuits. [Citation Graph (, )][DBLP]


  41. Deep sub-micron IDDQ testing: issues and solutions. [Citation Graph (, )][DBLP]


  42. A production-oriented measurement method for fast and exhaustive Iddq tests. [Citation Graph (, )][DBLP]


  43. Library mapping for memories. [Citation Graph (, )][DBLP]


  44. Architectural exploration and optimization for counter based hardware address generation. [Citation Graph (, )][DBLP]


  45. RTL synthesis with physical and controller information. [Citation Graph (, )][DBLP]


  46. Two-way partitioning based on direction vector [layout design]. [Citation Graph (, )][DBLP]


  47. Multi-layer chip-level global routing using an efficient graph-based Steiner tree heuristic. [Citation Graph (, )][DBLP]


  48. A gridless multi-layer router for standard cell circuits using CTM cells. [Citation Graph (, )][DBLP]


  49. A programmable boundary scan technique for board-level, parallel functional duplex march testing of word-oriented multiport static RAMs. [Citation Graph (, )][DBLP]


  50. Fault-secure shifter design: results and implementations. [Citation Graph (, )][DBLP]


  51. High-speed C-testable systolic array design for Galois-field inversion. [Citation Graph (, )][DBLP]


  52. Efficient and accurate testing of analog-to-digital converters using oscillation-test method. [Citation Graph (, )][DBLP]


  53. Built-in self-test methodology for A/D converters. [Citation Graph (, )][DBLP]


  54. Reconfigurable data converter as a building block for mixed-signal test. [Citation Graph (, )][DBLP]


  55. VHDL extensions for complex transmission line simulation. [Citation Graph (, )][DBLP]


  56. Acceleration of behavioral simulation on simulation specific machines. [Citation Graph (, )][DBLP]


  57. Exploiting temporal independence in distributed preemptive circuit simulation. [Citation Graph (, )][DBLP]


  58. Analogue layout generation by World Wide Web server-based agents. [Citation Graph (, )][DBLP]


  59. A performance-driven placement algorithm with simultaneous Place&Route optimization for analog ICs. [Citation Graph (, )][DBLP]


  60. An algorithm for numerical reference generation in symbolic analysis of large analog circuits. [Citation Graph (, )][DBLP]


  61. Adaptive least mean square behavioral power modeling. [Citation Graph (, )][DBLP]


  62. Fast power loss calculation for digital static CMOS circuits. [Citation Graph (, )][DBLP]


  63. Monte-Carlo approach for power estimation in sequential circuits. [Citation Graph (, )][DBLP]


  64. Hybrid symbolic-explicit techniques for the graph coloring problem. [Citation Graph (, )][DBLP]


  65. A constructive approach towards correctness of synthesis-application within retiming. [Citation Graph (, )][DBLP]


  66. A symbolic core approach to the formal verification of integrated mixed-mode applications. [Citation Graph (, )][DBLP]


  67. A novel methodology for designing TSC networks based on the parity bit code. [Citation Graph (, )][DBLP]


  68. Testing scheme for IC's clocks. [Citation Graph (, )][DBLP]


  69. A totally self-checking 1-out-of-3 code error indicator. [Citation Graph (, )][DBLP]


  70. Cone-based clustering heuristic for list-scheduling algorithms. [Citation Graph (, )][DBLP]


  71. Register synthesis for speculative computation. [Citation Graph (, )][DBLP]


  72. Multidimensional periodic scheduling: a solution approach. [Citation Graph (, )][DBLP]


  73. Multi-thread graph: a system model for real-time embedded software synthesis. [Citation Graph (, )][DBLP]


  74. PCC: a modeling technique for mixed control/data flow systems. [Citation Graph (, )][DBLP]


  75. Procedure cloning: a transformation for improved system-level functional partitioning. [Citation Graph (, )][DBLP]


  76. A fault diagnosis methodology for the UltraSPARCTM-I microprocessor. [Citation Graph (, )][DBLP]


  77. Improved diagnosis of realistic interconnect shorts. [Citation Graph (, )][DBLP]


  78. On improving genetic optimization based test generation. [Citation Graph (, )][DBLP]


  79. Symbolic synthesis of clock-gating logic for power optimization of control-oriented synchronous networks. [Citation Graph (, )][DBLP]


  80. Low power FSM design using Huffman-style encoding. [Citation Graph (, )][DBLP]


  81. Improving the accuracy of support-set finding method for power estimation of combinational circuits. [Citation Graph (, )][DBLP]


  82. Practical concurrent ASIC and system design and verification. [Citation Graph (, )][DBLP]


  83. A methodology for hardware architecture trade-off at different levels of abstraction. [Citation Graph (, )][DBLP]


  84. Synthesis of multi-rate and variable rate circuits for high speed telecommunications applications. [Citation Graph (, )][DBLP]


  85. Testability of 2-level AND/EXOR circuits. [Citation Graph (, )][DBLP]


  86. On the use of reset to increase the testability of interconnected finite-state machines. [Citation Graph (, )][DBLP]


  87. A new approach to build a low-level malicious fault list starting from high-level description and alternative graphs. [Citation Graph (, )][DBLP]


  88. On-chip analog output response compaction. [Citation Graph (, )][DBLP]


  89. A new quality estimation methodology for mixed-signal and analogue ICs. [Citation Graph (, )][DBLP]


  90. Compact structural test generation for analog macros. [Citation Graph (, )][DBLP]


  91. Accurate high level datapath power estimation. [Citation Graph (, )][DBLP]


  92. Maximizing the weighted switching activity in combinational CMOS circuits under the variable delay model. [Citation Graph (, )][DBLP]


  93. Internal power modelling and minimization in CMOS inverters. [Citation Graph (, )][DBLP]


  94. A new field programmable system-on-a-chip for mixed signal integration. [Citation Graph (, )][DBLP]


  95. PROPHID: a data-driven multi-processor architecture for high-performance DSP. [Citation Graph (, )][DBLP]


  96. ReCode: the design and re-design of the instruction codes for embedded instruction-set processors. [Citation Graph (, )][DBLP]


  97. A real-time smart sensor system for visual motion estimation. [Citation Graph (, )][DBLP]


  98. Full custom chip set for high speed serial communications up to 2.48 Gbit/s. [Citation Graph (, )][DBLP]


  99. An asynchronous architecture for digital signal processors. [Citation Graph (, )][DBLP]


  100. Test synthesis for DC test of switched-capacitors circuits. [Citation Graph (, )][DBLP]


  101. SISSSI-A tool for dynamic electro-thermal simulation of analog VLSI cells. [Citation Graph (, )][DBLP]


  102. Design of oscillation-based test structures for active RC filters. [Citation Graph (, )][DBLP]


  103. Using constraint logic programming in memory synthesis for general purpose computers. [Citation Graph (, )][DBLP]


  104. Optimal scheduling for fast systolic array implementations. [Citation Graph (, )][DBLP]


  105. Scheduling using mixed arithmetic: an ILP formulation. [Citation Graph (, )][DBLP]


  106. Performance verification using partial evaluation and interval analysis. [Citation Graph (, )][DBLP]


  107. Design and verification of the sequential systems automata using temporal logic specifications. [Citation Graph (, )][DBLP]


  108. Application independent module generation in analog layouts. [Citation Graph (, )][DBLP]


  109. A scheme for multiple on-chip signature checking for embedded SRAMs. [Citation Graph (, )][DBLP]


  110. Design of partially parallel scan chain. [Citation Graph (, )][DBLP]


  111. March LA: a test for linked memory faults. [Citation Graph (, )][DBLP]


  112. The input pattern fault model and its application. [Citation Graph (, )][DBLP]


  113. A monolithic off-chip IDDQ monitor. [Citation Graph (, )][DBLP]


  114. Extension of the boundary-scan architecture and new idea of BIST for more effective testing and self-testing of interconnections. [Citation Graph (, )][DBLP]

NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002