Conferences in DBLP
Has anything changed in electronic design since 1983? [Citation Graph (, )][DBLP ] Embedded systems design - Scientific challenges and work directions. [Citation Graph (, )][DBLP ] A low-power fat tree-based optical Network-On-Chip for multiprocessor system-on-chip. [Citation Graph (, )][DBLP ] SunFloor 3D: A tool for Networks On Chip topology synthesis for 3D systems on chips. [Citation Graph (, )][DBLP ] User-centric design space exploration for heterogeneous Network-on-Chip platforms. [Citation Graph (, )][DBLP ] A highly resilient routing algorithm for fault-tolerant NoCs. [Citation Graph (, )][DBLP ] Mapping of a film grain removal algorithm to a heterogeneous reconfigurable architecture. [Citation Graph (, )][DBLP ] An ILP formulation for task mapping and scheduling on multi-core architectures. [Citation Graph (, )][DBLP ] DPR in high energy physics. [Citation Graph (, )][DBLP ] A flexible layered architecture for accurate digital baseband algorithm development and verification. [Citation Graph (, )][DBLP ] Lifetime reliability-aware task allocation and scheduling for MPSoC platforms. [Citation Graph (, )][DBLP ] Integrated scheduling and synthesis of control applications on distributed embedded systems. [Citation Graph (, )][DBLP ] Towards no-cost adaptive MPSoC static schedules through exploitation of logical-to-physical core mapping latitude. [Citation Graph (, )][DBLP ] Pipelined data parallel task mapping/scheduling technique for MPSoC. [Citation Graph (, )][DBLP ] Joint logic restructuring and pin reordering against NBTI-induced performance degradation. [Citation Graph (, )][DBLP ] A self-adaptive system architecture to address transistor aging. [Citation Graph (, )][DBLP ] Masking timing errors on speed-paths in logic circuits. [Citation Graph (, )][DBLP ] WCRT algebra and interfaces for esterel-style synchronous processing. [Citation Graph (, )][DBLP ] Reliable mode changes in real-time systems with fixed priority or EDF scheduling. [Citation Graph (, )][DBLP ] Improved worst-case response-time calculations by upper-bound conditions. [Citation Graph (, )][DBLP ] A generalized scheduling approach for dynamic dataflow applications. [Citation Graph (, )][DBLP ] Optimizing data flow graphs to minimize hardware implementation. [Citation Graph (, )][DBLP ] Multi-clock Soc design using protocol conversion. [Citation Graph (, )][DBLP ] A formal approach to design space exploration of protocol converters. [Citation Graph (, )][DBLP ] Model-based synthesis and optimization of static multi-rate image processing algorithms. [Citation Graph (, )][DBLP ] Panel session - Consolidation, a modern "Moor of Venice" tale. [Citation Graph (, )][DBLP ] Variation resilient adaptive controller for subthreshold circuits. [Citation Graph (, )][DBLP ] Minimization of NBTI performance degradation using internal node control. [Citation Graph (, )][DBLP ] Physically clustered forward body biasing for variability compensation in nanometer CMOS design. [Citation Graph (, )][DBLP ] An event-guided approach to reducing voltage noise in processors. [Citation Graph (, )][DBLP ] Design and implementation of a database filter for BLAST acceleration. [Citation Graph (, )][DBLP ] A software-supported methodology for exploring interconnection architectures targeting 3-D FPGAs. [Citation Graph (, )][DBLP ] Priority-based packet communication on a bus-shaped structure for FPGA-systems. [Citation Graph (, )][DBLP ] Exploration of power reduction and performance enhancement in LEON3 processor with ESL reprogrammable eFPGA in processor pipeline and as a co-processor. [Citation Graph (, )][DBLP ] Functional qualification of TLM verification. [Citation Graph (, )][DBLP ] Solver technology for system-level to RTL equivalence checking. [Citation Graph (, )][DBLP ] A high-level debug environment for communication-centric debug. [Citation Graph (, )][DBLP ] Cache aware compression for processor debug support. [Citation Graph (, )][DBLP ] Fault insertion testing of a novel CPLD-based fail-safe system. [Citation Graph (, )][DBLP ] Test architecture design and optimization for three-dimensional SoCs. [Citation Graph (, )][DBLP ] A co-design approach for embedded system modeling and code generation with UML and MARTE. [Citation Graph (, )][DBLP ] Componentizing hardware/software interface design. [Citation Graph (, )][DBLP ] A UML frontend for IP-XACT-based IP management. [Citation Graph (, )][DBLP ] Evaluating UML2 modeling of IP-XACT objects for automatic MP-SoC integration onto FPGA. [Citation Graph (, )][DBLP ] Aelite: A flit-synchronous Network on Chip with composable and predictable services. [Citation Graph (, )][DBLP ] Configurable links for runtime adaptive on-chip communication. [Citation Graph (, )][DBLP ] Synthesis of low-overhead configurable source routing tables for network interfaces. [Citation Graph (, )][DBLP ] SCORES: A scalable and parametric streams-based communication architecture for modular reconfigurable systems. [Citation Graph (, )][DBLP ] Analog layout synthesis - Recent advances in topological approaches. [Citation Graph (, )][DBLP ] An accurate interconnect thermal model using equivalent transmission line circuit. [Citation Graph (, )][DBLP ] Analogue mixed signal simulation using spice and SystemC. [Citation Graph (, )][DBLP ] Reliability aware through silicon via planning for 3D stacked ICs. [Citation Graph (, )][DBLP ] A study on placement of post silicon clock tuning buffers for mitigating impact of process variation. [Citation Graph (, )][DBLP ] Analysis and optimization of NBTI induced clock skew in gated clock trees. [Citation Graph (, )][DBLP ] Bitstream relocation with local clock domains for partially reconfigurable FPGAs. [Citation Graph (, )][DBLP ] Parallel transistor level full-chip circuit simulation. [Citation Graph (, )][DBLP ] Performance-driven dual-rail insertion for chip-level pre-fabricated design. [Citation Graph (, )][DBLP ] Simulation framework for early phase exploration of SDR platforms: A case study of platform dimensioning. [Citation Graph (, )][DBLP ] Fast and accurate protocol specific bus modeling using TLM 2.0. [Citation Graph (, )][DBLP ] Incorporating graceful degradation into embedded system design. [Citation Graph (, )][DBLP ] Rewiring using IRredundancy Removal and Addition. [Citation Graph (, )][DBLP ] Gate replacement techniques for simultaneous leakage and aging optimization. [Citation Graph (, )][DBLP ] Enabling concurrent clock and power gating in an industrial design flow. [Citation Graph (, )][DBLP ] TRAM: A tool for Temperature and Reliability Aware Memory Design. [Citation Graph (, )][DBLP ] Aircraft integration real-time simulator modeling with AADL for architecture tradeoffs. [Citation Graph (, )][DBLP ] A low-cost SEE mitigation solution for soft-processors embedded in Systems on Pogrammable Chips. [Citation Graph (, )][DBLP ] Communication minimization for in-network processing in body sensor networks: A buffer assignment technique. [Citation Graph (, )][DBLP ] A MEMS reconfigurable quad-band Class-E Power Amplifier for GSM standard. [Citation Graph (, )][DBLP ] Power reduction of a 12-bit 40-MS/s pipeline ADC exploiting partial amplifier sharing. [Citation Graph (, )][DBLP ] PANEL SESSION - Is the second wave of HLS the one industry will surf on? [Citation Graph (, )][DBLP ] Analyzing the impact of process variations on parametric measurements: Novel models and applications. [Citation Graph (, )][DBLP ] On linewidth-based yield analysis for nanometer lithography. [Citation Graph (, )][DBLP ] Impact of voltage scaling on nanoscale SRAM reliability. [Citation Graph (, )][DBLP ] A file-system-aware FTL design for flash-memory storage systems. [Citation Graph (, )][DBLP ] FSAF: File system aware flash translation layer for NAND Flash Memories. [Citation Graph (, )][DBLP ] A set-based mapping strategy for flash-memory reliability enhancement. [Citation Graph (, )][DBLP ] Energy efficient multiprocessor task scheduling under input-dependent variation. [Citation Graph (, )][DBLP ] Program phase and runtime distribution-aware online DVFS for combined Vdd/Vbb scaling. [Citation Graph (, )][DBLP ] ORION 2.0: A fast and accurate NoC power and area model for early-stage design space exploration. [Citation Graph (, )][DBLP ] PANEL SESSION - Open source hardware IP, are you serious? [Citation Graph (, )][DBLP ] HOT TOPIC - Concurrent SoC development and end-to-end planning. [Citation Graph (, )][DBLP ] Nano-electronics challenge chip designers meet real nano-electronics in 2010s? [Citation Graph (, )][DBLP ] MTJ-based nonvolatile logic-in-memory circuit, future prospects and issues. [Citation Graph (, )][DBLP ] Imperfection-immune VLSI logic circuits using Carbon Nanotube Field Effect Transistors. [Citation Graph (, )][DBLP ] Reconfigurable circuit design with nanomaterials. [Citation Graph (, )][DBLP ] An architecture for secure software defined radio. [Citation Graph (, )][DBLP ] Optimizing the HW/SW boundary of an ECC SoC design using control hierarchy and distributed storage. [Citation Graph (, )][DBLP ] Hardware aging-based software metering. [Citation Graph (, )][DBLP ] On-chip communication architecture exploration for processor-pool-based MPSoC. [Citation Graph (, )][DBLP ] Combined system synthesis and communication architecture exploration for MPSoCs. [Citation Graph (, )][DBLP ] UMTS MPSoC design evaluation using a system level design framework. [Citation Graph (, )][DBLP ] Fault-tolerant average execution time optimization for general-purpose multi-processor system-on-chips. [Citation Graph (, )][DBLP ] Improving yield and reliability of chip multiprocessors. [Citation Graph (, )][DBLP ] A unified online Fault Detection scheme via checking of Stability Violation. [Citation Graph (, )][DBLP ] Statistical fault injection: Quantified error and confidence. [Citation Graph (, )][DBLP ] KAST: K-associative sector translation for NAND flash memory in real-time systems. [Citation Graph (, )][DBLP ] White box performance analysis considering static non-preemptive software scheduling. [Citation Graph (, )][DBLP ] Application specific performance indicators for quantitative evaluation of the timing behavior for embedded real-time systems. [Citation Graph (, )][DBLP ] Response-time analysis of arbitrarily activated tasks in multiprocessor systems with shared resources. [Citation Graph (, )][DBLP ] Light NUCA: A proposal for bridging the inter-cache latency gap. [Citation Graph (, )][DBLP ] ReSim, a trace-driven, reconfigurable ILP processor simulator. [Citation Graph (, )][DBLP ] Heterogeneous coarse-grained processing elements: A template architecture for embedded processing acceleration. [Citation Graph (, )][DBLP ] Algorithms for the automatic extension of an instruction-set. [Citation Graph (, )][DBLP ] Dimensioning heterogeneous MPSoCs via parallelism analysis. [Citation Graph (, )][DBLP ] MPSoCs run-time monitoring through Networks-on-Chip. [Citation Graph (, )][DBLP ] Assessing fat-tree topologies for regular network-on-chip design under nanoscale technology constraints. [Citation Graph (, )][DBLP ] A hybrid packet-circuit switched on-chip network based on SDM. [Citation Graph (, )][DBLP ] SecBus: Operating System controlled hierarchical page-based memory bus protection. [Citation Graph (, )][DBLP ] A link arbitration scheme for quality of service in a latency-optimized network-on-chip. [Citation Graph (, )][DBLP ] Flow regulation for on-chip communication. [Citation Graph (, )][DBLP ] Customizing IP cores for system-on-chip designs using extensive external don't-cares. [Citation Graph (, )][DBLP ] Extending IP-XACT to support an MDE based approach for SoC design. [Citation Graph (, )][DBLP ] Overcoming limitations of the SystemC data introspection. [Citation Graph (, )][DBLP ] Selective light Vth hopping (SLITH): Bridging the gap between runtime dynamic and leakage. [Citation Graph (, )][DBLP ] A power-efficient migration mechanism for D-NUCA caches. [Citation Graph (, )][DBLP ] Panel Session - Vertical integration versus disaggregation. [Citation Graph (, )][DBLP ] Trends and challenges in wireless application processors. [Citation Graph (, )][DBLP ] System-level process variability analysis and mitigation for 3D MPSoCs. [Citation Graph (, )][DBLP ] Co-design of signal, power, and thermal distribution networks for 3D ICs. [Citation Graph (, )][DBLP ] Design of compact imperfection-immune CNFET layouts for standard-cell-based logic synthesis. [Citation Graph (, )][DBLP ] Novel library of logic gates with ambipolar CNTFETs: Opportunities for multi-level logic synthesis. [Citation Graph (, )][DBLP ] Enhancing correlation electromagnetic attack using planar near-field cartography. [Citation Graph (, )][DBLP ] Evaluation on FPGA of triple rail logic robustness against DPA and DEMA. [Citation Graph (, )][DBLP ] Successful attack on an FPGA-based WDDL DES cryptoprocessor without place and route constraints. [Citation Graph (, )][DBLP ] Hardware evaluation of the stream cipher-based hash functions RadioGatún and irRUPT. [Citation Graph (, )][DBLP ] Architectural support for low overhead detection of memory violations. [Citation Graph (, )][DBLP ] Caspar: Hardware patching for multicore processors. [Citation Graph (, )][DBLP ] A new speculative addition architecture suitable for two's complement operations. [Citation Graph (, )][DBLP ] Limiting the number of dirty cache lines. [Citation Graph (, )][DBLP ] Contactless testing: Possibility or pipe-dream? [Citation Graph (, )][DBLP ] Analysis and optimization of fault-tolerant embedded systems with hardened processors. [Citation Graph (, )][DBLP ] On bounding response times under software transactional memory in distributed multiprocessor real-time systems. [Citation Graph (, )][DBLP ] An approximation scheme for energy-efficient scheduling of real-time tasks in heterogeneous multiprocessor systems. [Citation Graph (, )][DBLP ] A graph grammar based approach to automated multi-objective analog circuit design. [Citation Graph (, )][DBLP ] Massively multi-topology sizing of analog integrated circuits. [Citation Graph (, )][DBLP ] Improved performance and variation modelling for hierarchical-based optimisation of analogue integrated circuits. [Citation Graph (, )][DBLP ] Computation of IP3 using single-tone moments analysis. [Citation Graph (, )][DBLP ] Formal approaches to analog circuit verification. [Citation Graph (, )][DBLP ] Panel session - ESL methodology for SoC. [Citation Graph (, )][DBLP ] An overview of non-volatile memory technology and the implication for tools and architectures. [Citation Graph (, )][DBLP ] Power and performance of read-write aware Hybrid Caches with non-volatile memories. [Citation Graph (, )][DBLP ] Using non-volatile memory to save energy in servers. [Citation Graph (, )][DBLP ] aEqualized: A novel routing algorithm for the Spidergon Network On Chip. [Citation Graph (, )][DBLP ] Group-caching for NoC based multicore cache coherent systems. [Citation Graph (, )][DBLP ] A monitor interconnect and support subsystem for multicore processors. [Citation Graph (, )][DBLP ] A real-time application design methodology for MPSoCs. [Citation Graph (, )][DBLP ] Adaptive prefetching for shared cache based chip multiprocessors. [Citation Graph (, )][DBLP ] CUFFS: An instruction count based architectural framework for security of MPSoCs. [Citation Graph (, )][DBLP ] Design as you see FIT: System-level soft error analysis of sequential circuits. [Citation Graph (, )][DBLP ] Detecting errors using multi-cycle invariance information. [Citation Graph (, )][DBLP ] A novel approach to entirely integrate Virtual Test into test development flow. [Citation Graph (, )][DBLP ] Robust non-preemptive hard real-time scheduling for clustered multicore platforms. [Citation Graph (, )][DBLP ] Efficient OpenMP support and extensions for MPSoCs with explicitly managed memory hierarchy. [Citation Graph (, )][DBLP ] Using randomization to cope with circuit uncertainty. [Citation Graph (, )][DBLP ] Process variation aware thread mapping for Chip Multiprocessors. [Citation Graph (, )][DBLP ] Gate sizing for large cell-based designs. [Citation Graph (, )][DBLP ] Multi-domain clock skew scheduling-aware register placement to optimize clock distribution network. [Citation Graph (, )][DBLP ] Decoupling capacitor planning with analytical delay model on RLC power grid. [Citation Graph (, )][DBLP ] Package routability- and IR-drop-aware finger/pad assignment in chip-package co-design. [Citation Graph (, )][DBLP ] Learning early-stage platform dimensioning from late-stage timing verification. [Citation Graph (, )][DBLP ] The influence of real-time constraints on the design of FlexRay-based systems. [Citation Graph (, )][DBLP ] Time and memory tradeoffs in the implementation of AUTOSAR components. [Citation Graph (, )][DBLP ] Systolic like soft-detection architecture for 4×4 64-QAM MIMO system. [Citation Graph (, )][DBLP ] Co-simulation based platform for wireless protocols design explorations. [Citation Graph (, )][DBLP ] How to speed-up your NLFSR-based stream cipher. [Citation Graph (, )][DBLP ] A high performance reconfigurable Motion Estimation hardware architecture. [Citation Graph (, )][DBLP ] Partition-based exploration for reconfigurable JPEG designs. [Citation Graph (, )][DBLP ] Automated synthesis of streaming C applications to process networks in hardware. [Citation Graph (, )][DBLP ] Distributed sensor for steering wheel rip force measurement in driver fatigue detection. [Citation Graph (, )][DBLP ] Making DNA self-assembly error-proof: Attaining small growth error rates through embedded information redundancy. [Citation Graph (, )][DBLP ] Machine learning-based volume diagnosis. [Citation Graph (, )][DBLP ] Adaptive idleness distribution for non-uniform aging tolerance in MultiProcessor Systems-on-Chip. [Citation Graph (, )][DBLP ] Panel session - Architectures and integration for programmable SoC's. [Citation Graph (, )][DBLP ] Process Variation Aware SRAM/Cache for aggressive voltage-frequency scaling. [Citation Graph (, )][DBLP ] Single ended 6T SRAM with isolated read-port for low-power embedded systems. [Citation Graph (, )][DBLP ] System-level power/performance evaluation of 3D stacked DRAMs for mobile applications. [Citation Graph (, )][DBLP ] A novel DRAM architecture as a low leakage alternative for SRAM caches in a 3D interconnect context. [Citation Graph (, )][DBLP ] A case for multi-channel memories in video recording. [Citation Graph (, )][DBLP ] High level H.264/AVC video encoder parallelization for multiprocessor implementation. [Citation Graph (, )][DBLP ] Temperature-aware scheduler based on thermal behavior grouping in multicore systems. [Citation Graph (, )][DBLP ] Hardware/software co-design architecture for thermal management of chip multiprocessors. [Citation Graph (, )][DBLP ] Cross-architectural design space exploration tool for reconfigurable processors. [Citation Graph (, )][DBLP ] Automatically mapping applications to a self-reconfiguring platform. [Citation Graph (, )][DBLP ] OSSS+R: A framework for application level modelling and synthesis of reconfigurable systems. [Citation Graph (, )][DBLP ] Design optimizations to improve placeability of partial reconfiguration modules. [Citation Graph (, )][DBLP ] Automated data analysis solutions to silicon debug. [Citation Graph (, )][DBLP ] Efficient and accurate method for intra-gate defect diagnoses in nanometer technology and volume data. [Citation Graph (, )][DBLP ] Selection of a fault model for fault diagnosis based on unique responses. [Citation Graph (, )][DBLP ] Improving compressed test pattern generation for multiple scan chain failure diagnosis. [Citation Graph (, )][DBLP ] A case study in distributed deployment of embedded software for camera networks. [Citation Graph (, )][DBLP ] pTest: An adaptive testing tool for concurrent software on embedded multicore processors. [Citation Graph (, )][DBLP ] A generic platform for estimation of multi-threaded program performance on heterogeneous multiprocessors. [Citation Graph (, )][DBLP ] Networked embedded system applications design driven by an abstract middleware environment. [Citation Graph (, )][DBLP ] Health-care electronics The market, the challenges, the progress. [Citation Graph (, )][DBLP ] Design and implementation of scalable, transparent threads for multi-core media processor. [Citation Graph (, )][DBLP ] High data rate fully flexible SDR modem advanced configurable architecture & development methodology. [Citation Graph (, )][DBLP ] Cross-coupling in 65nm fully integrated EDGE System On Chip Design and cross-coupling prevention of complex 65nm SoC. [Citation Graph (, )][DBLP ] Embedded tutorial - Understanding multicore technologies. [Citation Graph (, )][DBLP ] Latency criticality aware on-chip communication. [Citation Graph (, )][DBLP ] In-network reorder buffer to improve overall NoC performance while resolving the in-order requirement problem. [Citation Graph (, )][DBLP ] An efficent dynamic multicast routing protocol for distributing traffic in NOCs. [Citation Graph (, )][DBLP ] Priority based forced requeue to reduce worst-case latencies for bursty traffic. [Citation Graph (, )][DBLP ] Optimizations of an application-level protocol for enhanced dependability in FlexRay. [Citation Graph (, )][DBLP ] Remote measurement of local oscillator drifts in FlexRay networks. [Citation Graph (, )][DBLP ] CAN+: A new backward-compatible Controller Area Network (CAN) protocol with up to 16× higher data rates. [Citation Graph (, )][DBLP ] Shock immunity enhancement via resonance damping in gyroscopes for automotive applications. [Citation Graph (, )][DBLP ] Integration of an advanced emergency call subsystem into a car-gateway platform. [Citation Graph (, )][DBLP ] Finite Precision bit-width allocation using SAT-Modulo Theory. [Citation Graph (, )][DBLP ] HLS-l: High-level synthesis of high performance latch-based circuits. [Citation Graph (, )][DBLP ] Automatic generation of streaming datapaths for arbitrary fixed permutations. [Citation Graph (, )][DBLP ] SEU-aware resource binding for modular redundancy based designs on FPGAs. [Citation Graph (, )][DBLP ] Generation of compact test sets with high defect coverage. [Citation Graph (, )][DBLP ] A scalable method for the generation of small test sets. [Citation Graph (, )][DBLP ] QC-Fill: An X-Fill method for quick-and-cool scan test. [Citation Graph (, )][DBLP ] Exploring parallelizations of applications for MPSoC platforms using MPA. [Citation Graph (, )][DBLP ] An MDE methodology for the development of high-integrity real-time systems. [Citation Graph (, )][DBLP ] Mode-based reconfiguration of critical software component architectures. [Citation Graph (, )][DBLP ] Towards a formal semantics for the AADL behavior annex. [Citation Graph (, )][DBLP ] On the efficient reduction of complete EM based parametric models. [Citation Graph (, )][DBLP ] Efficient compression and handling of current source model library waveforms. [Citation Graph (, )][DBLP ] New simulation methodology of 3D surface roughness loss for interconnects modeling. [Citation Graph (, )][DBLP ] An efficient decoupling capacitance optimization using piecewise polynomial models. [Citation Graph (, )][DBLP ] An automated flow for integrating hardware IP into the automotive systems engineering process. [Citation Graph (, )][DBLP ] Model Based Design needs high level synthesis - A collection of high level synthesis techniques to improve productivity and quality of results for model based electronic design. [Citation Graph (, )][DBLP ] EMC-aware design on a microcontroller for automotive applications. [Citation Graph (, )][DBLP ] Semiformal verification of temporal properties in automotive hardware dependent software. [Citation Graph (, )][DBLP ] On the relationship between stuck-at fault coverage and transition fault coverage. [Citation Graph (, )][DBLP ] System-level hardware-based protection of memories against soft-errors. [Citation Graph (, )][DBLP ] A study of the Single Event Effects impact on functional mapping within Flash-based FPGAs. [Citation Graph (, )][DBLP ] Finite precision processing in wireless applications. [Citation Graph (, )][DBLP ] A physical-location-aware X-filling method for IR-drop reduction in at-speed scan test. [Citation Graph (, )][DBLP ] Efficient reliability simulation of analog ICs including variability and time-varying stress. [Citation Graph (, )][DBLP ] A generic architecture of CCSDS Low Density Parity Check decoder for near-earth applications. [Citation Graph (, )][DBLP ] Property analysis and design understanding. [Citation Graph (, )][DBLP ] Test exploration and validation using transaction level models. [Citation Graph (, )][DBLP ] Heterogeneous multi-core platform for consumer multimedia applications. [Citation Graph (, )][DBLP ] Multi-core for mobile phones. [Citation Graph (, )][DBLP ] Strategic directions towards multicore application specific computing. [Citation Graph (, )][DBLP ] Energy-efficient spatially-adaptive clustering and routing in wireless sensor networks. [Citation Graph (, )][DBLP ] Online adaptation policy design for grid sensor networks with reconfigurable embedded nodes. [Citation Graph (, )][DBLP ] Defect-aware logic mapping for nanowire-based programmable logic arrays via satisfiability. [Citation Graph (, )][DBLP ] Debugging of Toffoli networks. [Citation Graph (, )][DBLP ] Cross-contamination avoidance for droplet routing in digital microfluidic biochips. [Citation Graph (, )][DBLP ] Error correction in single-hop wireless sensor networks - A case study. [Citation Graph (, )][DBLP ] Design of an application-specific instruction set processor for high-throughput and scalable FFT. [Citation Graph (, )][DBLP ] A novel LDPC decoder for DVB-S2 IP. [Citation Graph (, )][DBLP ] A flexible floating-point wavelet transform and wavelet packet processor. [Citation Graph (, )][DBLP ] On hierarchical statistical static timing analysis. [Citation Graph (, )][DBLP ] Increasing the accuracy of SAT-based debugging. [Citation Graph (, )][DBLP ] GCS: High-performance gate-level simulation with GPGPUs. [Citation Graph (, )][DBLP ] Trace signal selection for visibility enhancement in post-silicon validation. [Citation Graph (, )][DBLP ] A new design-for-test technique for SRAM core-cell stability faults. [Citation Graph (, )][DBLP ] Test cost reduction for multiple-voltage designs with bridge defects through Gate-Sizing. [Citation Graph (, )][DBLP ] A diagnosis algorithm for extreme space compaction. [Citation Graph (, )][DBLP ] Thermal-aware memory mapping in 3D designs. [Citation Graph (, )][DBLP ] Static analysis to mitigate soft errors in register files. [Citation Graph (, )][DBLP ] Using dynamic compilation for continuing execution under reduced memory availability. [Citation Graph (, )][DBLP ] A design methodology for fully reconfigurable Delta-Sigma data converters. [Citation Graph (, )][DBLP ] Optimal sizing of configurable devices to reduce variability in integrated circuits. [Citation Graph (, )][DBLP ] An automated design flow for vibration-based energy harvester systems. [Citation Graph (, )][DBLP ] Enhanced design of filterless class-D audio amplifier. [Citation Graph (, )][DBLP ] Panel session - Multicore, will Startups drive innovation? [Citation Graph (, )][DBLP ] Effectiveness of adaptive supply voltage and body bias as post-silicon variability compensation techniques for full-swing and low-swing on-chip communication channels. [Citation Graph (, )][DBLP ] Dynamic thermal management in 3D multicore architectures. [Citation Graph (, )][DBLP ] Energy minimization for real-time systems with non-convex and discrete operation modes. [Citation Graph (, )][DBLP ] Exploiting narrow-width values for thermal-aware register file designs. [Citation Graph (, )][DBLP ] Visual quality analysis for dynamic backlight scaling in LCD systems. [Citation Graph (, )][DBLP ] A parallel approach for high performance hardware design of intra prediction in H.264/AVC Video Codec. [Citation Graph (, )][DBLP ] Efficient constant-time entropy decoding for H.264. [Citation Graph (, )][DBLP ] Predictive models for multimedia applications power consumption based on use-case and OS level analysis. [Citation Graph (, )][DBLP ] Algebraic techniques to enhance common sub-expression elimination for polynomial system synthesis. [Citation Graph (, )][DBLP ] Sequential logic synthesis using symbolic bi-decomposition. [Citation Graph (, )][DBLP ] On decomposing Boolean functions via extended cofactoring. [Citation Graph (, )][DBLP ] Register placement for high-performance circuits. [Citation Graph (, )][DBLP ] Scalable Adaptive Scan (SAS). [Citation Graph (, )][DBLP ] LFSR-based test-data compression with self-stoppable seeds. [Citation Graph (, )][DBLP ] Seed selection in LFSR-reseeding-based test compression for the detection of small-delay defects. [Citation Graph (, )][DBLP ] A generic framework for scan capture power reduction in fixed-length symbol-based test compression environment. [Citation Graph (, )][DBLP ] Correct-by-construction generation of device drivers based on RTL testbenches. [Citation Graph (, )][DBLP ] Buffer minimization of real-time streaming applications scheduling on hybrid CPU/FPGA architectures. [Citation Graph (, )][DBLP ] A formal approach for specification-driven AMS behavioral model generation. [Citation Graph (, )][DBLP ] SC-DEVS: An efficient SystemC extension for the DEVS model of computation. [Citation Graph (, )][DBLP ] Exploiting clock skew scheduling for FPGA. [Citation Graph (, )][DBLP ] Accelerating FPGA-based emulation of quasi-cyclic LDPC codes with vector processing. [Citation Graph (, )][DBLP ] Runtime reconfiguration of custom instructions for real-time embedded systems. [Citation Graph (, )][DBLP ] Digital design at a crossroads How to make statistical design methodologies industrially relevant. [Citation Graph (, )][DBLP ] Performance optimal speed control of multi-core processors under thermal constraints. [Citation Graph (, )][DBLP ] Scalable compile-time scheduler for multi-core architectures. [Citation Graph (, )][DBLP ] Distributed peak power management for many-core architectures. [Citation Graph (, )][DBLP ] Generating the trace qualification configuration for MCDS from a high level language. [Citation Graph (, )][DBLP ] Dynamic and distributed frequency assignment for energy and latency constrained MP-SoC. [Citation Graph (, )][DBLP ] A MILP-based approach to path sensitization of embedded software. [Citation Graph (, )][DBLP ] An efficient and deterministic multi-tasking run-time environment for Ada and the Ravenscar profile on the Atmel AVR®32 UC3 microcontroller. [Citation Graph (, )][DBLP ] Toward a runtime system for reconfigurable computers: A virtualization approach. [Citation Graph (, )][DBLP ] Separate compilation and execution of imperative synchronous modules. [Citation Graph (, )][DBLP ] Programming MPSoC platforms: Road works ahead! [Citation Graph (, )][DBLP ] Faster SAT solving with better CNF generation. [Citation Graph (, )][DBLP ] Exploiting structure in an AIG based QBF solver. [Citation Graph (, )][DBLP ] An efficient path-oriented bitvector encoding width computation algorithm for bit-precise verification. [Citation Graph (, )][DBLP ] Algorithm-architecture co-design of soft-output ML MIMO detector for parallel application specific instruction set processors. [Citation Graph (, )][DBLP ] A low-power ASIP for IEEE 802.15.4a ultra-wideband impulse radio baseband processing. [Citation Graph (, )][DBLP ] ASIP-based flexible MMSE-IC Linear Equalizer for MIMO turbo-equalization applications. [Citation Graph (, )][DBLP ] Implementation of a reduced-lattice MIMO detector for OFDM Systems. [Citation Graph (, )][DBLP ] Increased accuracy through noise injection in abstract RTOS simulation. [Citation Graph (, )][DBLP ] Flexible energy-aware simulation of heterogenous wireless sensor networks. [Citation Graph (, )][DBLP ] Selective state retention design using symbolic simulation. [Citation Graph (, )][DBLP ] A loopback-based INL test method for D/A and A/D converters employing a stimulus identification technique. [Citation Graph (, )][DBLP ] A novel self-healing methodology for RF Amplifier circuits based on oscillation principles. [Citation Graph (, )][DBLP ] An approach to linear model-based testing for nonlinear cascaded mixed-signal systems. [Citation Graph (, )][DBLP ] Enrichment of limited training sets in machine-learning-based analog/RF test. [Citation Graph (, )][DBLP ] Speculative reduction-based scalable redundancy identification. [Citation Graph (, )][DBLP ] Scalable liveness checking via property-preserving transformations. [Citation Graph (, )][DBLP ] Speeding up model checking by exploiting explicit and hidden verification constraints. [Citation Graph (, )][DBLP ] Strengthening properties using abstraction refinement. [Citation Graph (, )][DBLP ] Sequential logic rectifications with approximate SPFDs. [Citation Graph (, )][DBLP ] Variable-latency design by function speculation. [Citation Graph (, )][DBLP ] Fixed points for multi-cycle path detection. [Citation Graph (, )][DBLP ] 