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Conferences in DBLP

Design, Automation, and Test in Europe (date)
2009 (conf/date/2009)

  1. Has anything changed in electronic design since 1983? [Citation Graph (, )][DBLP]

  2. Embedded systems design - Scientific challenges and work directions. [Citation Graph (, )][DBLP]

  3. A low-power fat tree-based optical Network-On-Chip for multiprocessor system-on-chip. [Citation Graph (, )][DBLP]

  4. SunFloor 3D: A tool for Networks On Chip topology synthesis for 3D systems on chips. [Citation Graph (, )][DBLP]

  5. User-centric design space exploration for heterogeneous Network-on-Chip platforms. [Citation Graph (, )][DBLP]

  6. A highly resilient routing algorithm for fault-tolerant NoCs. [Citation Graph (, )][DBLP]

  7. Mapping of a film grain removal algorithm to a heterogeneous reconfigurable architecture. [Citation Graph (, )][DBLP]

  8. An ILP formulation for task mapping and scheduling on multi-core architectures. [Citation Graph (, )][DBLP]

  9. DPR in high energy physics. [Citation Graph (, )][DBLP]

  10. A flexible layered architecture for accurate digital baseband algorithm development and verification. [Citation Graph (, )][DBLP]

  11. Lifetime reliability-aware task allocation and scheduling for MPSoC platforms. [Citation Graph (, )][DBLP]

  12. Integrated scheduling and synthesis of control applications on distributed embedded systems. [Citation Graph (, )][DBLP]

  13. Towards no-cost adaptive MPSoC static schedules through exploitation of logical-to-physical core mapping latitude. [Citation Graph (, )][DBLP]

  14. Pipelined data parallel task mapping/scheduling technique for MPSoC. [Citation Graph (, )][DBLP]

  15. Joint logic restructuring and pin reordering against NBTI-induced performance degradation. [Citation Graph (, )][DBLP]

  16. A self-adaptive system architecture to address transistor aging. [Citation Graph (, )][DBLP]

  17. Masking timing errors on speed-paths in logic circuits. [Citation Graph (, )][DBLP]

  18. WCRT algebra and interfaces for esterel-style synchronous processing. [Citation Graph (, )][DBLP]

  19. Reliable mode changes in real-time systems with fixed priority or EDF scheduling. [Citation Graph (, )][DBLP]

  20. Improved worst-case response-time calculations by upper-bound conditions. [Citation Graph (, )][DBLP]

  21. A generalized scheduling approach for dynamic dataflow applications. [Citation Graph (, )][DBLP]

  22. Optimizing data flow graphs to minimize hardware implementation. [Citation Graph (, )][DBLP]

  23. Multi-clock Soc design using protocol conversion. [Citation Graph (, )][DBLP]

  24. A formal approach to design space exploration of protocol converters. [Citation Graph (, )][DBLP]

  25. Model-based synthesis and optimization of static multi-rate image processing algorithms. [Citation Graph (, )][DBLP]

  26. Panel session - Consolidation, a modern "Moor of Venice" tale. [Citation Graph (, )][DBLP]

  27. Variation resilient adaptive controller for subthreshold circuits. [Citation Graph (, )][DBLP]

  28. Minimization of NBTI performance degradation using internal node control. [Citation Graph (, )][DBLP]

  29. Physically clustered forward body biasing for variability compensation in nanometer CMOS design. [Citation Graph (, )][DBLP]

  30. An event-guided approach to reducing voltage noise in processors. [Citation Graph (, )][DBLP]

  31. Design and implementation of a database filter for BLAST acceleration. [Citation Graph (, )][DBLP]

  32. A software-supported methodology for exploring interconnection architectures targeting 3-D FPGAs. [Citation Graph (, )][DBLP]

  33. Priority-based packet communication on a bus-shaped structure for FPGA-systems. [Citation Graph (, )][DBLP]

  34. Exploration of power reduction and performance enhancement in LEON3 processor with ESL reprogrammable eFPGA in processor pipeline and as a co-processor. [Citation Graph (, )][DBLP]

  35. Functional qualification of TLM verification. [Citation Graph (, )][DBLP]

  36. Solver technology for system-level to RTL equivalence checking. [Citation Graph (, )][DBLP]

  37. A high-level debug environment for communication-centric debug. [Citation Graph (, )][DBLP]

  38. Cache aware compression for processor debug support. [Citation Graph (, )][DBLP]

  39. Fault insertion testing of a novel CPLD-based fail-safe system. [Citation Graph (, )][DBLP]

  40. Test architecture design and optimization for three-dimensional SoCs. [Citation Graph (, )][DBLP]

  41. A co-design approach for embedded system modeling and code generation with UML and MARTE. [Citation Graph (, )][DBLP]

  42. Componentizing hardware/software interface design. [Citation Graph (, )][DBLP]

  43. A UML frontend for IP-XACT-based IP management. [Citation Graph (, )][DBLP]

  44. Evaluating UML2 modeling of IP-XACT objects for automatic MP-SoC integration onto FPGA. [Citation Graph (, )][DBLP]

  45. Aelite: A flit-synchronous Network on Chip with composable and predictable services. [Citation Graph (, )][DBLP]

  46. Configurable links for runtime adaptive on-chip communication. [Citation Graph (, )][DBLP]

  47. Synthesis of low-overhead configurable source routing tables for network interfaces. [Citation Graph (, )][DBLP]

  48. SCORES: A scalable and parametric streams-based communication architecture for modular reconfigurable systems. [Citation Graph (, )][DBLP]

  49. Analog layout synthesis - Recent advances in topological approaches. [Citation Graph (, )][DBLP]

  50. An accurate interconnect thermal model using equivalent transmission line circuit. [Citation Graph (, )][DBLP]

  51. Analogue mixed signal simulation using spice and SystemC. [Citation Graph (, )][DBLP]

  52. Reliability aware through silicon via planning for 3D stacked ICs. [Citation Graph (, )][DBLP]

  53. A study on placement of post silicon clock tuning buffers for mitigating impact of process variation. [Citation Graph (, )][DBLP]

  54. Analysis and optimization of NBTI induced clock skew in gated clock trees. [Citation Graph (, )][DBLP]

  55. Bitstream relocation with local clock domains for partially reconfigurable FPGAs. [Citation Graph (, )][DBLP]

  56. Parallel transistor level full-chip circuit simulation. [Citation Graph (, )][DBLP]

  57. Performance-driven dual-rail insertion for chip-level pre-fabricated design. [Citation Graph (, )][DBLP]

  58. Simulation framework for early phase exploration of SDR platforms: A case study of platform dimensioning. [Citation Graph (, )][DBLP]

  59. Fast and accurate protocol specific bus modeling using TLM 2.0. [Citation Graph (, )][DBLP]

  60. Incorporating graceful degradation into embedded system design. [Citation Graph (, )][DBLP]

  61. Rewiring using IRredundancy Removal and Addition. [Citation Graph (, )][DBLP]

  62. Gate replacement techniques for simultaneous leakage and aging optimization. [Citation Graph (, )][DBLP]

  63. Enabling concurrent clock and power gating in an industrial design flow. [Citation Graph (, )][DBLP]

  64. TRAM: A tool for Temperature and Reliability Aware Memory Design. [Citation Graph (, )][DBLP]

  65. Aircraft integration real-time simulator modeling with AADL for architecture tradeoffs. [Citation Graph (, )][DBLP]

  66. A low-cost SEE mitigation solution for soft-processors embedded in Systems on Pogrammable Chips. [Citation Graph (, )][DBLP]

  67. Communication minimization for in-network processing in body sensor networks: A buffer assignment technique. [Citation Graph (, )][DBLP]

  68. A MEMS reconfigurable quad-band Class-E Power Amplifier for GSM standard. [Citation Graph (, )][DBLP]

  69. Power reduction of a 12-bit 40-MS/s pipeline ADC exploiting partial amplifier sharing. [Citation Graph (, )][DBLP]

  70. PANEL SESSION - Is the second wave of HLS the one industry will surf on? [Citation Graph (, )][DBLP]

  71. Analyzing the impact of process variations on parametric measurements: Novel models and applications. [Citation Graph (, )][DBLP]

  72. On linewidth-based yield analysis for nanometer lithography. [Citation Graph (, )][DBLP]

  73. Impact of voltage scaling on nanoscale SRAM reliability. [Citation Graph (, )][DBLP]

  74. A file-system-aware FTL design for flash-memory storage systems. [Citation Graph (, )][DBLP]

  75. FSAF: File system aware flash translation layer for NAND Flash Memories. [Citation Graph (, )][DBLP]

  76. A set-based mapping strategy for flash-memory reliability enhancement. [Citation Graph (, )][DBLP]

  77. Energy efficient multiprocessor task scheduling under input-dependent variation. [Citation Graph (, )][DBLP]

  78. Program phase and runtime distribution-aware online DVFS for combined Vdd/Vbb scaling. [Citation Graph (, )][DBLP]

  79. ORION 2.0: A fast and accurate NoC power and area model for early-stage design space exploration. [Citation Graph (, )][DBLP]

  80. PANEL SESSION - Open source hardware IP, are you serious? [Citation Graph (, )][DBLP]

  81. HOT TOPIC - Concurrent SoC development and end-to-end planning. [Citation Graph (, )][DBLP]

  82. Nano-electronics challenge chip designers meet real nano-electronics in 2010s? [Citation Graph (, )][DBLP]

  83. MTJ-based nonvolatile logic-in-memory circuit, future prospects and issues. [Citation Graph (, )][DBLP]

  84. Imperfection-immune VLSI logic circuits using Carbon Nanotube Field Effect Transistors. [Citation Graph (, )][DBLP]

  85. Reconfigurable circuit design with nanomaterials. [Citation Graph (, )][DBLP]

  86. An architecture for secure software defined radio. [Citation Graph (, )][DBLP]

  87. Optimizing the HW/SW boundary of an ECC SoC design using control hierarchy and distributed storage. [Citation Graph (, )][DBLP]

  88. Hardware aging-based software metering. [Citation Graph (, )][DBLP]

  89. On-chip communication architecture exploration for processor-pool-based MPSoC. [Citation Graph (, )][DBLP]

  90. Combined system synthesis and communication architecture exploration for MPSoCs. [Citation Graph (, )][DBLP]

  91. UMTS MPSoC design evaluation using a system level design framework. [Citation Graph (, )][DBLP]

  92. Fault-tolerant average execution time optimization for general-purpose multi-processor system-on-chips. [Citation Graph (, )][DBLP]

  93. Improving yield and reliability of chip multiprocessors. [Citation Graph (, )][DBLP]

  94. A unified online Fault Detection scheme via checking of Stability Violation. [Citation Graph (, )][DBLP]

  95. Statistical fault injection: Quantified error and confidence. [Citation Graph (, )][DBLP]

  96. KAST: K-associative sector translation for NAND flash memory in real-time systems. [Citation Graph (, )][DBLP]

  97. White box performance analysis considering static non-preemptive software scheduling. [Citation Graph (, )][DBLP]

  98. Application specific performance indicators for quantitative evaluation of the timing behavior for embedded real-time systems. [Citation Graph (, )][DBLP]

  99. Response-time analysis of arbitrarily activated tasks in multiprocessor systems with shared resources. [Citation Graph (, )][DBLP]

  100. Light NUCA: A proposal for bridging the inter-cache latency gap. [Citation Graph (, )][DBLP]

  101. ReSim, a trace-driven, reconfigurable ILP processor simulator. [Citation Graph (, )][DBLP]

  102. Heterogeneous coarse-grained processing elements: A template architecture for embedded processing acceleration. [Citation Graph (, )][DBLP]

  103. Algorithms for the automatic extension of an instruction-set. [Citation Graph (, )][DBLP]

  104. Dimensioning heterogeneous MPSoCs via parallelism analysis. [Citation Graph (, )][DBLP]

  105. MPSoCs run-time monitoring through Networks-on-Chip. [Citation Graph (, )][DBLP]

  106. Assessing fat-tree topologies for regular network-on-chip design under nanoscale technology constraints. [Citation Graph (, )][DBLP]

  107. A hybrid packet-circuit switched on-chip network based on SDM. [Citation Graph (, )][DBLP]

  108. SecBus: Operating System controlled hierarchical page-based memory bus protection. [Citation Graph (, )][DBLP]

  109. A link arbitration scheme for quality of service in a latency-optimized network-on-chip. [Citation Graph (, )][DBLP]

  110. Flow regulation for on-chip communication. [Citation Graph (, )][DBLP]

  111. Customizing IP cores for system-on-chip designs using extensive external don't-cares. [Citation Graph (, )][DBLP]

  112. Extending IP-XACT to support an MDE based approach for SoC design. [Citation Graph (, )][DBLP]

  113. Overcoming limitations of the SystemC data introspection. [Citation Graph (, )][DBLP]

  114. Selective light Vth hopping (SLITH): Bridging the gap between runtime dynamic and leakage. [Citation Graph (, )][DBLP]

  115. A power-efficient migration mechanism for D-NUCA caches. [Citation Graph (, )][DBLP]

  116. Panel Session - Vertical integration versus disaggregation. [Citation Graph (, )][DBLP]

  117. Trends and challenges in wireless application processors. [Citation Graph (, )][DBLP]

  118. System-level process variability analysis and mitigation for 3D MPSoCs. [Citation Graph (, )][DBLP]

  119. Co-design of signal, power, and thermal distribution networks for 3D ICs. [Citation Graph (, )][DBLP]

  120. Design of compact imperfection-immune CNFET layouts for standard-cell-based logic synthesis. [Citation Graph (, )][DBLP]

  121. Novel library of logic gates with ambipolar CNTFETs: Opportunities for multi-level logic synthesis. [Citation Graph (, )][DBLP]

  122. Enhancing correlation electromagnetic attack using planar near-field cartography. [Citation Graph (, )][DBLP]

  123. Evaluation on FPGA of triple rail logic robustness against DPA and DEMA. [Citation Graph (, )][DBLP]

  124. Successful attack on an FPGA-based WDDL DES cryptoprocessor without place and route constraints. [Citation Graph (, )][DBLP]

  125. Hardware evaluation of the stream cipher-based hash functions RadioGatún and irRUPT. [Citation Graph (, )][DBLP]

  126. Architectural support for low overhead detection of memory violations. [Citation Graph (, )][DBLP]

  127. Caspar: Hardware patching for multicore processors. [Citation Graph (, )][DBLP]

  128. A new speculative addition architecture suitable for two's complement operations. [Citation Graph (, )][DBLP]

  129. Limiting the number of dirty cache lines. [Citation Graph (, )][DBLP]

  130. Contactless testing: Possibility or pipe-dream? [Citation Graph (, )][DBLP]

  131. Analysis and optimization of fault-tolerant embedded systems with hardened processors. [Citation Graph (, )][DBLP]

  132. On bounding response times under software transactional memory in distributed multiprocessor real-time systems. [Citation Graph (, )][DBLP]

  133. An approximation scheme for energy-efficient scheduling of real-time tasks in heterogeneous multiprocessor systems. [Citation Graph (, )][DBLP]

  134. A graph grammar based approach to automated multi-objective analog circuit design. [Citation Graph (, )][DBLP]

  135. Massively multi-topology sizing of analog integrated circuits. [Citation Graph (, )][DBLP]

  136. Improved performance and variation modelling for hierarchical-based optimisation of analogue integrated circuits. [Citation Graph (, )][DBLP]

  137. Computation of IP3 using single-tone moments analysis. [Citation Graph (, )][DBLP]

  138. Formal approaches to analog circuit verification. [Citation Graph (, )][DBLP]

  139. Panel session - ESL methodology for SoC. [Citation Graph (, )][DBLP]

  140. An overview of non-volatile memory technology and the implication for tools and architectures. [Citation Graph (, )][DBLP]

  141. Power and performance of read-write aware Hybrid Caches with non-volatile memories. [Citation Graph (, )][DBLP]

  142. Using non-volatile memory to save energy in servers. [Citation Graph (, )][DBLP]

  143. aEqualized: A novel routing algorithm for the Spidergon Network On Chip. [Citation Graph (, )][DBLP]

  144. Group-caching for NoC based multicore cache coherent systems. [Citation Graph (, )][DBLP]

  145. A monitor interconnect and support subsystem for multicore processors. [Citation Graph (, )][DBLP]

  146. A real-time application design methodology for MPSoCs. [Citation Graph (, )][DBLP]

  147. Adaptive prefetching for shared cache based chip multiprocessors. [Citation Graph (, )][DBLP]

  148. CUFFS: An instruction count based architectural framework for security of MPSoCs. [Citation Graph (, )][DBLP]

  149. Design as you see FIT: System-level soft error analysis of sequential circuits. [Citation Graph (, )][DBLP]

  150. Detecting errors using multi-cycle invariance information. [Citation Graph (, )][DBLP]

  151. A novel approach to entirely integrate Virtual Test into test development flow. [Citation Graph (, )][DBLP]

  152. Robust non-preemptive hard real-time scheduling for clustered multicore platforms. [Citation Graph (, )][DBLP]

  153. Efficient OpenMP support and extensions for MPSoCs with explicitly managed memory hierarchy. [Citation Graph (, )][DBLP]

  154. Using randomization to cope with circuit uncertainty. [Citation Graph (, )][DBLP]

  155. Process variation aware thread mapping for Chip Multiprocessors. [Citation Graph (, )][DBLP]

  156. Gate sizing for large cell-based designs. [Citation Graph (, )][DBLP]

  157. Multi-domain clock skew scheduling-aware register placement to optimize clock distribution network. [Citation Graph (, )][DBLP]

  158. Decoupling capacitor planning with analytical delay model on RLC power grid. [Citation Graph (, )][DBLP]

  159. Package routability- and IR-drop-aware finger/pad assignment in chip-package co-design. [Citation Graph (, )][DBLP]

  160. Learning early-stage platform dimensioning from late-stage timing verification. [Citation Graph (, )][DBLP]

  161. The influence of real-time constraints on the design of FlexRay-based systems. [Citation Graph (, )][DBLP]

  162. Time and memory tradeoffs in the implementation of AUTOSAR components. [Citation Graph (, )][DBLP]

  163. Systolic like soft-detection architecture for 4×4 64-QAM MIMO system. [Citation Graph (, )][DBLP]

  164. Co-simulation based platform for wireless protocols design explorations. [Citation Graph (, )][DBLP]

  165. How to speed-up your NLFSR-based stream cipher. [Citation Graph (, )][DBLP]

  166. A high performance reconfigurable Motion Estimation hardware architecture. [Citation Graph (, )][DBLP]

  167. Partition-based exploration for reconfigurable JPEG designs. [Citation Graph (, )][DBLP]

  168. Automated synthesis of streaming C applications to process networks in hardware. [Citation Graph (, )][DBLP]

  169. Distributed sensor for steering wheel rip force measurement in driver fatigue detection. [Citation Graph (, )][DBLP]

  170. Making DNA self-assembly error-proof: Attaining small growth error rates through embedded information redundancy. [Citation Graph (, )][DBLP]

  171. Machine learning-based volume diagnosis. [Citation Graph (, )][DBLP]

  172. Adaptive idleness distribution for non-uniform aging tolerance in MultiProcessor Systems-on-Chip. [Citation Graph (, )][DBLP]

  173. Panel session - Architectures and integration for programmable SoC's. [Citation Graph (, )][DBLP]

  174. Process Variation Aware SRAM/Cache for aggressive voltage-frequency scaling. [Citation Graph (, )][DBLP]

  175. Single ended 6T SRAM with isolated read-port for low-power embedded systems. [Citation Graph (, )][DBLP]

  176. System-level power/performance evaluation of 3D stacked DRAMs for mobile applications. [Citation Graph (, )][DBLP]

  177. A novel DRAM architecture as a low leakage alternative for SRAM caches in a 3D interconnect context. [Citation Graph (, )][DBLP]

  178. A case for multi-channel memories in video recording. [Citation Graph (, )][DBLP]

  179. High level H.264/AVC video encoder parallelization for multiprocessor implementation. [Citation Graph (, )][DBLP]

  180. Temperature-aware scheduler based on thermal behavior grouping in multicore systems. [Citation Graph (, )][DBLP]

  181. Hardware/software co-design architecture for thermal management of chip multiprocessors. [Citation Graph (, )][DBLP]

  182. Cross-architectural design space exploration tool for reconfigurable processors. [Citation Graph (, )][DBLP]

  183. Automatically mapping applications to a self-reconfiguring platform. [Citation Graph (, )][DBLP]

  184. OSSS+R: A framework for application level modelling and synthesis of reconfigurable systems. [Citation Graph (, )][DBLP]

  185. Design optimizations to improve placeability of partial reconfiguration modules. [Citation Graph (, )][DBLP]

  186. Automated data analysis solutions to silicon debug. [Citation Graph (, )][DBLP]

  187. Efficient and accurate method for intra-gate defect diagnoses in nanometer technology and volume data. [Citation Graph (, )][DBLP]

  188. Selection of a fault model for fault diagnosis based on unique responses. [Citation Graph (, )][DBLP]

  189. Improving compressed test pattern generation for multiple scan chain failure diagnosis. [Citation Graph (, )][DBLP]

  190. A case study in distributed deployment of embedded software for camera networks. [Citation Graph (, )][DBLP]

  191. pTest: An adaptive testing tool for concurrent software on embedded multicore processors. [Citation Graph (, )][DBLP]

  192. A generic platform for estimation of multi-threaded program performance on heterogeneous multiprocessors. [Citation Graph (, )][DBLP]

  193. Networked embedded system applications design driven by an abstract middleware environment. [Citation Graph (, )][DBLP]

  194. Health-care electronics The market, the challenges, the progress. [Citation Graph (, )][DBLP]

  195. Design and implementation of scalable, transparent threads for multi-core media processor. [Citation Graph (, )][DBLP]

  196. High data rate fully flexible SDR modem advanced configurable architecture & development methodology. [Citation Graph (, )][DBLP]

  197. Cross-coupling in 65nm fully integrated EDGE System On Chip Design and cross-coupling prevention of complex 65nm SoC. [Citation Graph (, )][DBLP]

  198. Embedded tutorial - Understanding multicore technologies. [Citation Graph (, )][DBLP]

  199. Latency criticality aware on-chip communication. [Citation Graph (, )][DBLP]

  200. In-network reorder buffer to improve overall NoC performance while resolving the in-order requirement problem. [Citation Graph (, )][DBLP]

  201. An efficent dynamic multicast routing protocol for distributing traffic in NOCs. [Citation Graph (, )][DBLP]

  202. Priority based forced requeue to reduce worst-case latencies for bursty traffic. [Citation Graph (, )][DBLP]

  203. Optimizations of an application-level protocol for enhanced dependability in FlexRay. [Citation Graph (, )][DBLP]

  204. Remote measurement of local oscillator drifts in FlexRay networks. [Citation Graph (, )][DBLP]

  205. CAN+: A new backward-compatible Controller Area Network (CAN) protocol with up to 16× higher data rates. [Citation Graph (, )][DBLP]

  206. Shock immunity enhancement via resonance damping in gyroscopes for automotive applications. [Citation Graph (, )][DBLP]

  207. Integration of an advanced emergency call subsystem into a car-gateway platform. [Citation Graph (, )][DBLP]

  208. Finite Precision bit-width allocation using SAT-Modulo Theory. [Citation Graph (, )][DBLP]

  209. HLS-l: High-level synthesis of high performance latch-based circuits. [Citation Graph (, )][DBLP]

  210. Automatic generation of streaming datapaths for arbitrary fixed permutations. [Citation Graph (, )][DBLP]

  211. SEU-aware resource binding for modular redundancy based designs on FPGAs. [Citation Graph (, )][DBLP]

  212. Generation of compact test sets with high defect coverage. [Citation Graph (, )][DBLP]

  213. A scalable method for the generation of small test sets. [Citation Graph (, )][DBLP]

  214. QC-Fill: An X-Fill method for quick-and-cool scan test. [Citation Graph (, )][DBLP]

  215. Exploring parallelizations of applications for MPSoC platforms using MPA. [Citation Graph (, )][DBLP]

  216. An MDE methodology for the development of high-integrity real-time systems. [Citation Graph (, )][DBLP]

  217. Mode-based reconfiguration of critical software component architectures. [Citation Graph (, )][DBLP]

  218. Towards a formal semantics for the AADL behavior annex. [Citation Graph (, )][DBLP]

  219. On the efficient reduction of complete EM based parametric models. [Citation Graph (, )][DBLP]

  220. Efficient compression and handling of current source model library waveforms. [Citation Graph (, )][DBLP]

  221. New simulation methodology of 3D surface roughness loss for interconnects modeling. [Citation Graph (, )][DBLP]

  222. An efficient decoupling capacitance optimization using piecewise polynomial models. [Citation Graph (, )][DBLP]

  223. An automated flow for integrating hardware IP into the automotive systems engineering process. [Citation Graph (, )][DBLP]

  224. Model Based Design needs high level synthesis - A collection of high level synthesis techniques to improve productivity and quality of results for model based electronic design. [Citation Graph (, )][DBLP]

  225. EMC-aware design on a microcontroller for automotive applications. [Citation Graph (, )][DBLP]

  226. Semiformal verification of temporal properties in automotive hardware dependent software. [Citation Graph (, )][DBLP]

  227. On the relationship between stuck-at fault coverage and transition fault coverage. [Citation Graph (, )][DBLP]

  228. System-level hardware-based protection of memories against soft-errors. [Citation Graph (, )][DBLP]

  229. A study of the Single Event Effects impact on functional mapping within Flash-based FPGAs. [Citation Graph (, )][DBLP]

  230. Finite precision processing in wireless applications. [Citation Graph (, )][DBLP]

  231. A physical-location-aware X-filling method for IR-drop reduction in at-speed scan test. [Citation Graph (, )][DBLP]

  232. Efficient reliability simulation of analog ICs including variability and time-varying stress. [Citation Graph (, )][DBLP]

  233. A generic architecture of CCSDS Low Density Parity Check decoder for near-earth applications. [Citation Graph (, )][DBLP]

  234. Property analysis and design understanding. [Citation Graph (, )][DBLP]

  235. Test exploration and validation using transaction level models. [Citation Graph (, )][DBLP]

  236. Heterogeneous multi-core platform for consumer multimedia applications. [Citation Graph (, )][DBLP]

  237. Multi-core for mobile phones. [Citation Graph (, )][DBLP]

  238. Strategic directions towards multicore application specific computing. [Citation Graph (, )][DBLP]

  239. Energy-efficient spatially-adaptive clustering and routing in wireless sensor networks. [Citation Graph (, )][DBLP]

  240. Online adaptation policy design for grid sensor networks with reconfigurable embedded nodes. [Citation Graph (, )][DBLP]

  241. Defect-aware logic mapping for nanowire-based programmable logic arrays via satisfiability. [Citation Graph (, )][DBLP]

  242. Debugging of Toffoli networks. [Citation Graph (, )][DBLP]

  243. Cross-contamination avoidance for droplet routing in digital microfluidic biochips. [Citation Graph (, )][DBLP]

  244. Error correction in single-hop wireless sensor networks - A case study. [Citation Graph (, )][DBLP]

  245. Design of an application-specific instruction set processor for high-throughput and scalable FFT. [Citation Graph (, )][DBLP]

  246. A novel LDPC decoder for DVB-S2 IP. [Citation Graph (, )][DBLP]

  247. A flexible floating-point wavelet transform and wavelet packet processor. [Citation Graph (, )][DBLP]

  248. On hierarchical statistical static timing analysis. [Citation Graph (, )][DBLP]

  249. Increasing the accuracy of SAT-based debugging. [Citation Graph (, )][DBLP]

  250. GCS: High-performance gate-level simulation with GPGPUs. [Citation Graph (, )][DBLP]

  251. Trace signal selection for visibility enhancement in post-silicon validation. [Citation Graph (, )][DBLP]

  252. A new design-for-test technique for SRAM core-cell stability faults. [Citation Graph (, )][DBLP]

  253. Test cost reduction for multiple-voltage designs with bridge defects through Gate-Sizing. [Citation Graph (, )][DBLP]

  254. A diagnosis algorithm for extreme space compaction. [Citation Graph (, )][DBLP]

  255. Thermal-aware memory mapping in 3D designs. [Citation Graph (, )][DBLP]

  256. Static analysis to mitigate soft errors in register files. [Citation Graph (, )][DBLP]

  257. Using dynamic compilation for continuing execution under reduced memory availability. [Citation Graph (, )][DBLP]

  258. A design methodology for fully reconfigurable Delta-Sigma data converters. [Citation Graph (, )][DBLP]

  259. Optimal sizing of configurable devices to reduce variability in integrated circuits. [Citation Graph (, )][DBLP]

  260. An automated design flow for vibration-based energy harvester systems. [Citation Graph (, )][DBLP]

  261. Enhanced design of filterless class-D audio amplifier. [Citation Graph (, )][DBLP]

  262. Panel session - Multicore, will Startups drive innovation? [Citation Graph (, )][DBLP]

  263. Effectiveness of adaptive supply voltage and body bias as post-silicon variability compensation techniques for full-swing and low-swing on-chip communication channels. [Citation Graph (, )][DBLP]

  264. Dynamic thermal management in 3D multicore architectures. [Citation Graph (, )][DBLP]

  265. Energy minimization for real-time systems with non-convex and discrete operation modes. [Citation Graph (, )][DBLP]

  266. Exploiting narrow-width values for thermal-aware register file designs. [Citation Graph (, )][DBLP]

  267. Visual quality analysis for dynamic backlight scaling in LCD systems. [Citation Graph (, )][DBLP]

  268. A parallel approach for high performance hardware design of intra prediction in H.264/AVC Video Codec. [Citation Graph (, )][DBLP]

  269. Efficient constant-time entropy decoding for H.264. [Citation Graph (, )][DBLP]

  270. Predictive models for multimedia applications power consumption based on use-case and OS level analysis. [Citation Graph (, )][DBLP]

  271. Algebraic techniques to enhance common sub-expression elimination for polynomial system synthesis. [Citation Graph (, )][DBLP]

  272. Sequential logic synthesis using symbolic bi-decomposition. [Citation Graph (, )][DBLP]

  273. On decomposing Boolean functions via extended cofactoring. [Citation Graph (, )][DBLP]

  274. Register placement for high-performance circuits. [Citation Graph (, )][DBLP]

  275. Scalable Adaptive Scan (SAS). [Citation Graph (, )][DBLP]

  276. LFSR-based test-data compression with self-stoppable seeds. [Citation Graph (, )][DBLP]

  277. Seed selection in LFSR-reseeding-based test compression for the detection of small-delay defects. [Citation Graph (, )][DBLP]

  278. A generic framework for scan capture power reduction in fixed-length symbol-based test compression environment. [Citation Graph (, )][DBLP]

  279. Correct-by-construction generation of device drivers based on RTL testbenches. [Citation Graph (, )][DBLP]

  280. Buffer minimization of real-time streaming applications scheduling on hybrid CPU/FPGA architectures. [Citation Graph (, )][DBLP]

  281. A formal approach for specification-driven AMS behavioral model generation. [Citation Graph (, )][DBLP]

  282. SC-DEVS: An efficient SystemC extension for the DEVS model of computation. [Citation Graph (, )][DBLP]

  283. Exploiting clock skew scheduling for FPGA. [Citation Graph (, )][DBLP]

  284. Accelerating FPGA-based emulation of quasi-cyclic LDPC codes with vector processing. [Citation Graph (, )][DBLP]

  285. Runtime reconfiguration of custom instructions for real-time embedded systems. [Citation Graph (, )][DBLP]

  286. Digital design at a crossroads How to make statistical design methodologies industrially relevant. [Citation Graph (, )][DBLP]

  287. Performance optimal speed control of multi-core processors under thermal constraints. [Citation Graph (, )][DBLP]

  288. Scalable compile-time scheduler for multi-core architectures. [Citation Graph (, )][DBLP]

  289. Distributed peak power management for many-core architectures. [Citation Graph (, )][DBLP]

  290. Generating the trace qualification configuration for MCDS from a high level language. [Citation Graph (, )][DBLP]

  291. Dynamic and distributed frequency assignment for energy and latency constrained MP-SoC. [Citation Graph (, )][DBLP]

  292. A MILP-based approach to path sensitization of embedded software. [Citation Graph (, )][DBLP]

  293. An efficient and deterministic multi-tasking run-time environment for Ada and the Ravenscar profile on the Atmel AVR®32 UC3 microcontroller. [Citation Graph (, )][DBLP]

  294. Toward a runtime system for reconfigurable computers: A virtualization approach. [Citation Graph (, )][DBLP]

  295. Separate compilation and execution of imperative synchronous modules. [Citation Graph (, )][DBLP]

  296. Programming MPSoC platforms: Road works ahead! [Citation Graph (, )][DBLP]

  297. Faster SAT solving with better CNF generation. [Citation Graph (, )][DBLP]

  298. Exploiting structure in an AIG based QBF solver. [Citation Graph (, )][DBLP]

  299. An efficient path-oriented bitvector encoding width computation algorithm for bit-precise verification. [Citation Graph (, )][DBLP]

  300. Algorithm-architecture co-design of soft-output ML MIMO detector for parallel application specific instruction set processors. [Citation Graph (, )][DBLP]

  301. A low-power ASIP for IEEE 802.15.4a ultra-wideband impulse radio baseband processing. [Citation Graph (, )][DBLP]

  302. ASIP-based flexible MMSE-IC Linear Equalizer for MIMO turbo-equalization applications. [Citation Graph (, )][DBLP]

  303. Implementation of a reduced-lattice MIMO detector for OFDM Systems. [Citation Graph (, )][DBLP]

  304. Increased accuracy through noise injection in abstract RTOS simulation. [Citation Graph (, )][DBLP]

  305. Flexible energy-aware simulation of heterogenous wireless sensor networks. [Citation Graph (, )][DBLP]

  306. Selective state retention design using symbolic simulation. [Citation Graph (, )][DBLP]

  307. A loopback-based INL test method for D/A and A/D converters employing a stimulus identification technique. [Citation Graph (, )][DBLP]

  308. A novel self-healing methodology for RF Amplifier circuits based on oscillation principles. [Citation Graph (, )][DBLP]

  309. An approach to linear model-based testing for nonlinear cascaded mixed-signal systems. [Citation Graph (, )][DBLP]

  310. Enrichment of limited training sets in machine-learning-based analog/RF test. [Citation Graph (, )][DBLP]

  311. Speculative reduction-based scalable redundancy identification. [Citation Graph (, )][DBLP]

  312. Scalable liveness checking via property-preserving transformations. [Citation Graph (, )][DBLP]

  313. Speeding up model checking by exploiting explicit and hidden verification constraints. [Citation Graph (, )][DBLP]

  314. Strengthening properties using abstraction refinement. [Citation Graph (, )][DBLP]

  315. Sequential logic rectifications with approximate SPFDs. [Citation Graph (, )][DBLP]

  316. Variable-latency design by function speculation. [Citation Graph (, )][DBLP]

  317. Fixed points for multi-cycle path detection. [Citation Graph (, )][DBLP]

System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
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