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Conferences in DBLP

Design, Automation, and Test in Europe (date)
2010 (conf/date/2010)


  1. All things are connected. [Citation Graph (, )][DBLP]


  2. Wireless communication - successful differentiation on standard technology by innovation. [Citation Graph (, )][DBLP]


  3. Loosely Time-Triggered Architectures for Cyber-Physical Systems. [Citation Graph (, )][DBLP]


  4. Energy-efficient real-time task scheduling with temperature-dependent leakage. [Citation Graph (, )][DBLP]


  5. Predicting energy and performance overhead of Real-Time Operating Systems. [Citation Graph (, )][DBLP]


  6. Temperature-aware idle time distribution for energy optimization with dynamic voltage scaling. [Citation Graph (, )][DBLP]


  7. Multicore soft error rate stabilization using adaptive dual modular redundancy. [Citation Graph (, )][DBLP]


  8. A fully-asynchronous low-power framework for GALS NoC integration. [Citation Graph (, )][DBLP]


  9. Supporting Distributed Shared Memory on multi-core Network-on-Chips using a dual microcoded controller. [Citation Graph (, )][DBLP]


  10. MEDEA: a hybrid shared-memory/message-passing multiprocessor NoC-based architecture. [Citation Graph (, )][DBLP]


  11. AgeSim: A simulation framework for evaluating the lifetime reliability of processor-based SoCs. [Citation Graph (, )][DBLP]


  12. Statistical SRAM analysis for yield enhancement. [Citation Graph (, )][DBLP]


  13. Cost-effective IR-drop failure identification and yield recovery through a failure-adaptive test scheme. [Citation Graph (, )][DBLP]


  14. Scan based methodology for reliable state retention power gating designs. [Citation Graph (, )][DBLP]


  15. TLM+ modeling of embedded HW/SW systems. [Citation Graph (, )][DBLP]


  16. Scenario extraction for a refined timing-analysis of automotive network topologies. [Citation Graph (, )][DBLP]


  17. Graphical Model Debugger Framework for embedded systems. [Citation Graph (, )][DBLP]


  18. IP routing processing with graphic processors. [Citation Graph (, )][DBLP]


  19. An efficient distributed memory interface for many-core platform with 3D stacked DRAM. [Citation Graph (, )][DBLP]


  20. Efficient OpenMP data mapping for multicore platforms with vertically stacked memory. [Citation Graph (, )][DBLP]


  21. Energy-efficient variable-flow liquid cooling in 3D stacked architectures. [Citation Graph (, )][DBLP]


  22. Optimization of an on-chip active cooling system based on thin-film thermoelectric coolers. [Citation Graph (, )][DBLP]


  23. Are we there yet? Has IP block assembly become as easy as LEGO? [Citation Graph (, )][DBLP]


  24. Temperature-aware dynamic resource provisioning in a power-optimized datacenter. [Citation Graph (, )][DBLP]


  25. From transistors to MEMS: Throughput-aware power gating in CMOS circuits. [Citation Graph (, )][DBLP]


  26. Energy- and endurance-aware design of phase change memory caches. [Citation Graph (, )][DBLP]


  27. Evaluation and design exploration of solar harvested-energy prediction algorithm. [Citation Graph (, )][DBLP]


  28. A nondestructive self-reference scheme for Spin-Transfer Torque Random Access Memory (STT-RAM). [Citation Graph (, )][DBLP]


  29. Pseudo-CMOS: A novel design style for flexible electronics. [Citation Graph (, )][DBLP]


  30. Spinto: High-performance energy minimization in spin glasses. [Citation Graph (, )][DBLP]


  31. TSV redundancy: Architecture and design issues in 3D IC. [Citation Graph (, )][DBLP]


  32. A GPU based implementation of Center-Surround Distribution Distance for feature extraction and matching. [Citation Graph (, )][DBLP]


  33. Parallel subdivision surface rendering and animation on the Cell BE processor. [Citation Graph (, )][DBLP]


  34. Heterogeneous vs homogeneous MPSoC approaches for a Mobile LTE modem. [Citation Graph (, )][DBLP]


  35. Recursion-driven parallel code generation for multi-core platforms. [Citation Graph (, )][DBLP]


  36. An industrial design space exploration framework for supporting run-time resource management on multi-core systems. [Citation Graph (, )][DBLP]


  37. Stretching the limits of FPGA SerDes for enhanced ATE performance. [Citation Graph (, )][DBLP]


  38. Multi-temperature testing for core-based system-on-chip. [Citation Graph (, )][DBLP]


  39. Memory testing with a RISC microcontroller. [Citation Graph (, )][DBLP]


  40. Constant-time admission control for Deadline Monotonic tasks. [Citation Graph (, )][DBLP]


  41. Exploiting inter-event stream correlations between output event streams of non-preemptively scheduled tasks. [Citation Graph (, )][DBLP]


  42. Transition-aware real-time task scheduling for reconfigurable embedded systems. [Citation Graph (, )][DBLP]


  43. IVF: Characterizing the vulnerability of microprocessor structures to intermittent faults. [Citation Graph (, )][DBLP]


  44. Aging-resilient design of pipelined architectures using novel detection and correction circuits. [Citation Graph (, )][DBLP]


  45. An integrated framework for joint design space exploration of microarchitecture and circuits. [Citation Graph (, )][DBLP]


  46. Challenges in the design of automotive software. [Citation Graph (, )][DBLP]


  47. AUTOSAR and the automotive tool chain. [Citation Graph (, )][DBLP]


  48. AUTOSAR basic software for complex control units. [Citation Graph (, )][DBLP]


  49. High-fidelity markovian power model for protocols. [Citation Graph (, )][DBLP]


  50. Energy-performance design space exploration in SMT architectures exploiting selective load value predictions. [Citation Graph (, )][DBLP]


  51. Error resilience of intra-die and inter-die communication with 3D spidergon STNoC. [Citation Graph (, )][DBLP]


  52. Towards a chip level reliability simulator for copper/low-k backend processes. [Citation Graph (, )][DBLP]


  53. NBTI modeling in the framework of temperature variation. [Citation Graph (, )][DBLP]


  54. RunAssert: A non-intrusive run-time assertion for parallel programs debugging. [Citation Graph (, )][DBLP]


  55. An RDL-configurable 3D memory tier to replace on-chip SRAM. [Citation Graph (, )][DBLP]


  56. GentleCool: Cooling aware proactive workload scheduling in multi-machine systems. [Citation Graph (, )][DBLP]


  57. Timing modeling for digital sub-threshold circuits. [Citation Graph (, )][DBLP]


  58. Power consumption of logic circuits in ambipolar carbon nanotube technology. [Citation Graph (, )][DBLP]


  59. Reversible logic synthesis through ant colony optimization. [Citation Graph (, )][DBLP]


  60. Low-power FinFET circuit synthesis using surface orientation optimization. [Citation Graph (, )][DBLP]


  61. Implementing digital logic with sinusoidal supplies. [Citation Graph (, )][DBLP]


  62. A reconfigurable multiprocessor architecture for a reliable face recognition implementation. [Citation Graph (, )][DBLP]


  63. A systematic approach to the test of combined HW/SW systems. [Citation Graph (, )][DBLP]


  64. A new approach for adaptive failure diagnostics based on emulation test. [Citation Graph (, )][DBLP]


  65. Integrated end-to-end timing analysis of networked AUTOSAR-compliant systems. [Citation Graph (, )][DBLP]


  66. Scalable stochastic processors. [Citation Graph (, )][DBLP]


  67. AVGS-Mux style: A novel technology and device independent technique for reducing power and compensating process variations in FPGA fabrics. [Citation Graph (, )][DBLP]


  68. On the efficacy of write-assist techniques in low voltage nanoscale SRAMs. [Citation Graph (, )][DBLP]


  69. Optimizing the power delivery network in dynamically voltage scaled systems with uncertain power mode transition times. [Citation Graph (, )][DBLP]


  70. Run-time spatial resource management for real-time applications on heterogeneous MPSoCs. [Citation Graph (, )][DBLP]


  71. Rapid runtime estimation methods for pipelined MPSoCs. [Citation Graph (, )][DBLP]


  72. Automatic workload generation for system-level exploration based on modified GCC compiler. [Citation Graph (, )][DBLP]


  73. A rapid prototyping system for error-resilient multi-processor systems-on-chip. [Citation Graph (, )][DBLP]


  74. Learning-based adaptation to applications and environments in a reconfigurable Network-on-Chip. [Citation Graph (, )][DBLP]


  75. Application-specific memory performance of a heterogeneous reconfigurable architecture. [Citation Graph (, )][DBLP]


  76. A reconfigurable hardware for one bit transform based multiple reference frame Motion Estimation. [Citation Graph (, )][DBLP]


  77. Ultra-high throughput string matching for Deep Packet Inspection. [Citation Graph (, )][DBLP]


  78. A HMMER hardware accelerator using divergences. [Citation Graph (, )][DBLP]


  79. Proactive NBTI mitigation for busy functional units in out-of-order microprocessors. [Citation Graph (, )][DBLP]


  80. Circuit propagation delay estimation through multivariate regression-based modeling under spatio-temporal variability. [Citation Graph (, )][DBLP]


  81. Analytical model for TDDB-based performance degradation in combinational logic. [Citation Graph (, )][DBLP]


  82. Static and dynamic stability improvement strategies for 6T CMOS low-power SRAMs. [Citation Graph (, )][DBLP]


  83. Test front loading in early stages of automotive software development based on AUTOSAR. [Citation Graph (, )][DBLP]


  84. A proposal for real-time interfaces in SPEEDS. [Citation Graph (, )][DBLP]


  85. Scenario-based analysis and synthesis of real-time systems using uppaal. [Citation Graph (, )][DBLP]


  86. Variation-aware interconnect extraction using statistical moment preserving model order reduction. [Citation Graph (, )][DBLP]


  87. Efficient 3D high-frequency impedance extraction for general interconnects and inductors above a layered substrate. [Citation Graph (, )][DBLP]


  88. HORUS - high-dimensional Model Order Reduction via low moment-matching upgraded sampling. [Citation Graph (, )][DBLP]


  89. On passivity of the super node algorithm for EM modeling of interconnect systems. [Citation Graph (, )][DBLP]


  90. The road to energy-efficient systems: From hardware-driven to software-defined. [Citation Graph (, )][DBLP]


  91. Vacuity analysis for property qualification by mutation of checkers. [Citation Graph (, )][DBLP]


  92. An abstraction-guided simulation approach using Markov models for microprocessor verification. [Citation Graph (, )][DBLP]


  93. Efficient decision ordering techniques for SAT-based test generation. [Citation Graph (, )][DBLP]


  94. DEW: A fast level 1 cache simulation approach for embedded processors with FIFO replacement policy. [Citation Graph (, )][DBLP]


  95. FlashPower: A detailed power model for NAND flash memory. [Citation Graph (, )][DBLP]


  96. A power optimization method for CMOS Op-Amps using sub-space based geometric programming. [Citation Graph (, )][DBLP]


  97. Power gating design for standard-cell-like structured ASICs. [Citation Graph (, )][DBLP]


  98. Dual-Vth leakage reduction with Fast Clock Skew Scheduling Enhancement. [Citation Graph (, )][DBLP]


  99. An high voltage CMOS voltage regulator for automotive alternators with programmable functionalities and full reverse polarity capability. [Citation Graph (, )][DBLP]


  100. Design of an automotive traffic sign recognition system targeting a multi-core SoC implementation. [Citation Graph (, )][DBLP]


  101. Simulation-based verification of the MOST NetInterface specification revision 3.0. [Citation Graph (, )][DBLP]


  102. Holistic simulation of FlexRay networks by using run-time model switching. [Citation Graph (, )][DBLP]


  103. Computing robustness of FlexRay schedules to uncertainties in design parameters. [Citation Graph (, )][DBLP]


  104. Adapting to adaptive testing. [Citation Graph (, )][DBLP]


  105. Using filesystem virtualization to avoid metadata bottlenecks. [Citation Graph (, )][DBLP]


  106. An accurate system architecture refinement methodology with mixed abstraction-level virtual platform. [Citation Graph (, )][DBLP]


  107. Non-intrusive virtualization management using libvirt. [Citation Graph (, )][DBLP]


  108. Process variation and temperature-aware reliability management. [Citation Graph (, )][DBLP]


  109. Optimized self-tuning for circuit aging. [Citation Graph (, )][DBLP]


  110. Investigating the impact of NBTI on different power saving cache strategies. [Citation Graph (, )][DBLP]


  111. Energy-oriented dynamic SPM allocation based on time-slotted Cache conflict graph. [Citation Graph (, )][DBLP]


  112. Enhanced Q-learning algorithm for dynamic power management with performance constraint. [Citation Graph (, )][DBLP]


  113. Parallel simulation of systemC TLM 2.0 compliant MPSoC on SMP workstations. [Citation Graph (, )][DBLP]


  114. High-speed clock recovery for low-cost FPGAs. [Citation Graph (, )][DBLP]


  115. Demonstration of an in-band reconfiguration data distribution and network node reconfiguration. [Citation Graph (, )][DBLP]


  116. Programmable aging sensor for automotive safety-critical applications. [Citation Graph (, )][DBLP]


  117. Passive reduced order modeling of multiport interconnects via semidefinite programming. [Citation Graph (, )][DBLP]


  118. GoldMine: Automatic assertion generation using data mining and static analysis. [Citation Graph (, )][DBLP]


  119. Assertion-based verification of RTOS properties. [Citation Graph (, )][DBLP]


  120. Post-placement temperature reduction techniques. [Citation Graph (, )][DBLP]


  121. Clock gating approaches by IOEX graphs and cluster efficiency plots. [Citation Graph (, )][DBLP]


  122. Timing modeling and analysis for AUTOSAR-based software development - a case study. [Citation Graph (, )][DBLP]


  123. Design of a real-time optimized emulation method. [Citation Graph (, )][DBLP]


  124. Capturing intrinsic parameter fluctuations using the PSP compact model. [Citation Graph (, )][DBLP]


  125. Power efficient voltage islanding for Systems-on-chip from a floorplanning perspective. [Citation Graph (, )][DBLP]


  126. Always energy-optimal microscopic wireless systems. [Citation Graph (, )][DBLP]


  127. Hardware / software design challenges of low-power sensor nodes for condition monitoring. [Citation Graph (, )][DBLP]


  128. Security aspects in 6lowPan networks. [Citation Graph (, )][DBLP]


  129. Monolithically stackable hybrid FPGA. [Citation Graph (, )][DBLP]


  130. Spintronic memristor devices and application. [Citation Graph (, )][DBLP]


  131. Compact model of memristors and its application in computing systems. [Citation Graph (, )][DBLP]


  132. Design space exploration of a mesochronous link for cost-effective and flexible GALS NOCs. [Citation Graph (, )][DBLP]


  133. A methodology for the characterization of process variation in NoC links. [Citation Graph (, )][DBLP]


  134. PhoenixSim: A simulator for physical-layer analysis of chip-scale photonic interconnection networks. [Citation Graph (, )][DBLP]


  135. An 11.6-19.3mW 0.375-13.6GHz CMOS frequency synthesizer with rail-to-rail operation. [Citation Graph (, )][DBLP]


  136. A compact digital amplitude modulator in 90nm CMOS. [Citation Graph (, )][DBLP]


  137. A 14 bit, 280 kS/s cyclic ADC with 100 dB SFDR. [Citation Graph (, )][DBLP]


  138. Ultra-low power mixed-signal design platform using subthreshold source-coupled circuits. [Citation Graph (, )][DBLP]


  139. Clock skew scheduling for soft-error-tolerant sequential circuits. [Citation Graph (, )][DBLP]


  140. HW/SW co-detection of transient and permanent faults with fast recovery in statically scheduled data paths. [Citation Graph (, )][DBLP]


  141. Scalable codeword generation for coupled buses. [Citation Graph (, )][DBLP]


  142. An adaptive code rate EDAC scheme for random access memory. [Citation Graph (, )][DBLP]


  143. Worst case delay analysis for memory interference in multicore systems. [Citation Graph (, )][DBLP]


  144. Throughput modeling to evaluate process merging transformations in polyhedral process networks. [Citation Graph (, )][DBLP]


  145. Trace-based KPN composability analysis for mapping simultaneous applications to MPSoC platforms. [Citation Graph (, )][DBLP]


  146. Bounding the shared resource load for the performance analysis of multiprocessor systems. [Citation Graph (, )][DBLP]


  147. An error-correcting unordered code and hardware support for robust asynchronous global communication. [Citation Graph (, )][DBLP]


  148. Large-scale Boolean matching. [Citation Graph (, )][DBLP]


  149. KL-Cuts: A new approach for logic synthesis targeting multiple output blocks. [Citation Graph (, )][DBLP]


  150. RALF: Reliability Analysis for Logic Faults - An exact algorithm and its applications. [Citation Graph (, )][DBLP]


  151. Panel 6.8: The challenges of heterogeneous multicore debug. [Citation Graph (, )][DBLP]


  152. Why design must change: Rethinking digital design. [Citation Graph (, )][DBLP]


  153. Low power design of the X-GOLD® SDR 20 baseband processor. [Citation Graph (, )][DBLP]


  154. Low power mobile internet devices using LTE technology. [Citation Graph (, )][DBLP]


  155. A black box method for stability analysis of arbitrary SRAM cell structures. [Citation Graph (, )][DBLP]


  156. Loop flattening & spherical sampling: Highly efficient model reduction techniques for SRAM yield analysis. [Citation Graph (, )][DBLP]


  157. Practical Monte-Carlo based timing yield estimation of digital circuits. [Citation Graph (, )][DBLP]


  158. Statistical static timing analysis using Markov chain Monte Carlo. [Citation Graph (, )][DBLP]


  159. KAHRISMA: A novel Hypermorphic Reconfigurable-Instruction-Set Multi-grained-Array architecture. [Citation Graph (, )][DBLP]


  160. A reconfigurable cache memory with heterogeneous banks. [Citation Graph (, )][DBLP]


  161. Evaluation of runtime task mapping heuristics with rSesame - a case study. [Citation Graph (, )][DBLP]


  162. VAPRES: A Virtual Architecture for Partially Reconfigurable Embedded Systems. [Citation Graph (, )][DBLP]


  163. pSHS: A scalable parallel software implementation of Montgomery multiplication for multicore systems. [Citation Graph (, )][DBLP]


  164. BCDL: A high speed balanced DPL for FPGA with global precharge and no early evaluation. [Citation Graph (, )][DBLP]


  165. Fault-based attack of RSA authentication. [Citation Graph (, )][DBLP]


  166. Detecting/preventing information leakage on the memory bus due to malicious hardware. [Citation Graph (, )][DBLP]


  167. An embedded platform for privacy-friendly road charging applications. [Citation Graph (, )][DBLP]


  168. Defect aware X-filling for low-power scan testing. [Citation Graph (, )][DBLP]


  169. Parallel X-fault simulation with critical path tracing technique. [Citation Graph (, )][DBLP]


  170. Diagnosis of multiple arbitrary faults with mask and reinforcement effect. [Citation Graph (, )][DBLP]


  171. Skewed pipelining for parallel simulink simulations. [Citation Graph (, )][DBLP]


  172. An efficient and complete approach for throughput-maximal SDF allocation and scheduling on multi-core platforms. [Citation Graph (, )][DBLP]


  173. A software update service with self-protection capabilities. [Citation Graph (, )][DBLP]


  174. Bitstream processing for embedded systems using C++ metaprogramming. [Citation Graph (, )][DBLP]


  175. Increasing PCM main memory lifetime. [Citation Graph (, )][DBLP]


  176. Dueling CLOCK: Adaptive cache replacement policy based on the CLOCK algorithm. [Citation Graph (, )][DBLP]


  177. A memory- and time-efficient on-chip TCAM minimizer for IP lookup. [Citation Graph (, )][DBLP]


  178. Panel Session - Who Is Closing the embedded software design gap? [Citation Graph (, )][DBLP]


  179. Accelerating Lightpath setup via broadcasting in binary-tree waveguide in Optical NoCs. [Citation Graph (, )][DBLP]


  180. A High-Voltage Low-Power DC-DC buck regulator for automotive applications. [Citation Graph (, )][DBLP]


  181. SimTag: Exploiting tag bits similarity to improve the reliability of the data caches. [Citation Graph (, )][DBLP]


  182. The split register file. [Citation Graph (, )][DBLP]


  183. Multithreaded code from synchronous programs: Extracting independent threads for OpenMP. [Citation Graph (, )][DBLP]


  184. RMOT: Recursion in model order for task execution time estimation in a software pipeline. [Citation Graph (, )][DBLP]


  185. Approximate logic synthesis for error tolerant applications. [Citation Graph (, )][DBLP]


  186. Automatic microarchitectural pipelining. [Citation Graph (, )][DBLP]


  187. Non-linear Operating Point Statistical Analysis for Local Variations in logic timing at low voltage. [Citation Graph (, )][DBLP]


  188. Dynamically reconfigurable register file for a softcore VLIW processor. [Citation Graph (, )][DBLP]


  189. FPGA-based adaptive computing for correlated multi-stream processing. [Citation Graph (, )][DBLP]


  190. Far Correlation-based EMA with a precharacterized leakage model. [Citation Graph (, )][DBLP]


  191. Improved countermeasure against Address-bit DPA for ECC scalar multiplication. [Citation Graph (, )][DBLP]


  192. Enabling efficient post-silicon debug by clustering of hardware-assertions. [Citation Graph (, )][DBLP]


  193. Constrained Power Management: Application to a multimedia mobile platform. [Citation Graph (, )][DBLP]


  194. Mapping scientific applications on a large-scale data-path accelerator implemented by single-flux quantum (SFQ) circuits. [Citation Graph (, )][DBLP]


  195. MB-LITE: A robust, light-weight soft-core implementation of the MicroBlaze architecture. [Citation Graph (, )][DBLP]


  196. Automatic pipelining from transactional datapath specifications. [Citation Graph (, )][DBLP]


  197. Increasing the power efficiency of PCs by improving the hardware/OS interaction. [Citation Graph (, )][DBLP]


  198. Optimize your power and performance yields and regain those sleepless nights. [Citation Graph (, )][DBLP]


  199. Digital statistical analysis using VHDL. [Citation Graph (, )][DBLP]


  200. A resilience roadmap. [Citation Graph (, )][DBLP]


  201. Vision for cross-layer optimization to address the dual challenges of energy and reliability. [Citation Graph (, )][DBLP]


  202. Design techniques for cross-layer resilience. [Citation Graph (, )][DBLP]


  203. Cross-layer resilience challenges: Metrics and optimization. [Citation Graph (, )][DBLP]


  204. Pareto efficient design for reconfigurable streaming applications on CPU/FPGAs. [Citation Graph (, )][DBLP]


  205. Automated bottleneck-driven design-space exploration of media processing systems. [Citation Graph (, )][DBLP]


  206. Using Transaction Level Modeling techniques for wireless sensor network simulation. [Citation Graph (, )][DBLP]


  207. RTOS-aware refinement for TLM2.0-based HW/SW designs. [Citation Graph (, )][DBLP]


  208. Power Variance Analysis breaks a masked ASIC implementation of AES. [Citation Graph (, )][DBLP]


  209. Novel Physical Unclonable Function with process and environmental variations. [Citation Graph (, )][DBLP]


  210. Ultra low-power 12-bit SAR ADC for RFID applications. [Citation Graph (, )][DBLP]


  211. A flexible UWB Transmitter for breast cancer detection imaging systems. [Citation Graph (, )][DBLP]


  212. A portable multi-pitch e-drum based on printed flexible pressure sensors. [Citation Graph (, )][DBLP]


  213. Computation of yield-optimized Pareto fronts for analog integrated circuit specifications. [Citation Graph (, )][DBLP]


  214. Variability-aware reliability simulation of mixed-signal ICs with quasi-linear complexity. [Citation Graph (, )][DBLP]


  215. A general mathematical model of probabilistic ripple-carry adders. [Citation Graph (, )][DBLP]


  216. An accurate and efficient yield optimization method for analog circuits based on computing budget allocation and memetic search technique. [Citation Graph (, )][DBLP]


  217. Reuse-aware modulo scheduling for stream processors. [Citation Graph (, )][DBLP]


  218. Compilation of stream programs for multicore processors that incorporate scratchpad memories. [Citation Graph (, )][DBLP]


  219. Partitioning and allocation of scratch-pad memory for priority-based preemptive multi-task systems. [Citation Graph (, )][DBLP]


  220. A special-purpose compiler for look-up table and code generation for function evaluation. [Citation Graph (, )][DBLP]


  221. General behavioral thermal modeling and characterization for multi-core microprocessor design. [Citation Graph (, )][DBLP]


  222. On the construction of guaranteed passive macromodels for high-speed channels. [Citation Graph (, )][DBLP]


  223. Extended Hamiltonian Pencil for passivity assessment and enforcement for S-parameter systems. [Citation Graph (, )][DBLP]


  224. Equivalent circuit modeling of multilayered power/ground planes for fast transient simulation. [Citation Graph (, )][DBLP]


  225. Carbon nanotube circuits: Living with imperfections and variations. [Citation Graph (, )][DBLP]


  226. Properties of and improvements to time-domain dynamic thermal analysis algorithms. [Citation Graph (, )][DBLP]


  227. Towards assertion-based verification of heterogeneous system designs. [Citation Graph (, )][DBLP]


  228. Automatic generation of software TLM in multiple abstraction layers for efficient HW/SW co-simulation. [Citation Graph (, )][DBLP]


  229. Modeling constructs and kernel for parallel simulation of accuracy adaptive TLMs. [Citation Graph (, )][DBLP]


  230. Efficient High-Level modeling in the networking domain. [Citation Graph (, )][DBLP]


  231. UML design for dynamically reconfigurable multiprocessor embedded systems. [Citation Graph (, )][DBLP]


  232. Closing the gap between UML-based modeling, simulation and synthesis of combined HW/SW systems. [Citation Graph (, )][DBLP]


  233. Formal semantics for PSL modeling layer and application to the verification of transactional models. [Citation Graph (, )][DBLP]


  234. COTS-based applications in space avionics. [Citation Graph (, )][DBLP]


  235. Worst-case end-to-end delay analysis of an avionics AFDX network. [Citation Graph (, )][DBLP]


  236. Integration, cooling and packaging issues for aerospace equipments. [Citation Graph (, )][DBLP]


  237. A new placement algorithm for the mitigation of multiple cell upsets in SRAM-based FPGAs. [Citation Graph (, )][DBLP]


  238. Reducing the storage requirements of a test sequence by using a background vector. [Citation Graph (, )][DBLP]


  239. BISD: Scan-based Built-In self-diagnosis. [Citation Graph (, )][DBLP]


  240. Algorithms to maximize yield and enhance yield/area of pipeline circuitry by insertion of switches and redundant modules. [Citation Graph (, )][DBLP]


  241. A generalized control-flow-aware pattern recognition algorithm for behavioral synthesis. [Citation Graph (, )][DBLP]


  242. Behavioral level dual-vth design for reduced leakage power with thermal awareness. [Citation Graph (, )][DBLP]


  243. Coordinated resource optimization in behavioral synthesis. [Citation Graph (, )][DBLP]


  244. A methodology for propagating design tolerances to shape tolerances for use in manufacturing. [Citation Graph (, )][DBLP]


  245. Enhancing double-patterning detailed routing with lazy coloring and within-path conflict avoidance. [Citation Graph (, )][DBLP]


  246. Efficient representation, stratification, and compression of variational CSM library waveforms using Robust Principle Component Analysis. [Citation Graph (, )][DBLP]


  247. Exploiting local logic structures to optimize multi-core SoC floorplanning. [Citation Graph (, )][DBLP]


  248. Cost modeling and cycle-accurate co-simulation of heterogeneous multiprocessor systems. [Citation Graph (, )][DBLP]


  249. Differential Power Analysis enhancement with statistical preprocessing. [Citation Graph (, )][DBLP]


  250. Correlation controlled sampling for efficient variability analysis of analog circuits. [Citation Graph (, )][DBLP]


  251. Formal verification of analog circuits in the presence of noise and process variation. [Citation Graph (, )][DBLP]


  252. Toward optimized code generation through model-based optimization. [Citation Graph (, )][DBLP]


  253. Path-based scheduling in a hardware compiler. [Citation Graph (, )][DBLP]


  254. Optimization of FIR filter to improve eye diagram for general transmission line systems. [Citation Graph (, )][DBLP]


  255. On signalling over Through-Silicon Via (TSV) interconnects in 3-D Integrated Circuits. [Citation Graph (, )][DBLP]


  256. Interconnect delay and slew metrics using the beta distribution. [Citation Graph (, )][DBLP]


  257. Accurate timed RTOS model for transaction level modeling. [Citation Graph (, )][DBLP]


  258. A modeling method by eliminating execution traces for performance evaluation. [Citation Graph (, )][DBLP]


  259. Verifying UML/OCL models using Boolean satisfiability. [Citation Graph (, )][DBLP]


  260. SCOC3: a space computer on a chip. [Citation Graph (, )][DBLP]


  261. High temperature polymer capacitors for aerospace applications. [Citation Graph (, )][DBLP]


  262. An on-chip clock generation scheme for faster-than-at-speed delay testing. [Citation Graph (, )][DBLP]


  263. Construction of dual mode components for reconfiguration aware high-level synthesis. [Citation Graph (, )][DBLP]


  264. Optimizing Data-Flow Graphs with min/max, adding and relational operations. [Citation Graph (, )][DBLP]


  265. Optimization of the bias current network for accurate on-chip thermal monitoring. [Citation Graph (, )][DBLP]


  266. SAT based multi-net rip-up-and-reroute for manufacturing hotspot removal. [Citation Graph (, )][DBLP]


  267. NIM- a noise index model to estimate delay discrepancies between silicon and simulation. [Citation Graph (, )][DBLP]


  268. Panel: First commandment at least, do nothing well! [Citation Graph (, )][DBLP]


  269. SigNet: Network-on-chip filtering for coarse vector directories. [Citation Graph (, )][DBLP]


  270. Feedback control for providing QoS in NoC based multicores. [Citation Graph (, )][DBLP]


  271. Exploiting multiple switch libraries in topology synthesis of on-chip interconnection network. [Citation Graph (, )][DBLP]


  272. Low-complexity high throughput VLSI architecture of soft-output ML MIMO detector. [Citation Graph (, )][DBLP]


  273. A low cost multi-standard near-optimal soft-output sphere decoder: Algorithm and architecture. [Citation Graph (, )][DBLP]


  274. Leveraging application-level requirements in the design of a NoC for a 4G SoC - a case study. [Citation Graph (, )][DBLP]


  275. Domain specific architecture for next generation wireless communication. [Citation Graph (, )][DBLP]


  276. A 150Mbit/s 3GPP LTE Turbo code decoder. [Citation Graph (, )][DBLP]


  277. High-quality pattern selection for screening small-delay defects considering process variations and crosstalk. [Citation Graph (, )][DBLP]


  278. Layout-aware pseudo-functional testing for critical paths considering power supply noise effects. [Citation Graph (, )][DBLP]


  279. On reset based functional broadside tests. [Citation Graph (, )][DBLP]


  280. Scheduling for energy efficiency and fault tolerance in hard real-time systems. [Citation Graph (, )][DBLP]


  281. Scoped identifiers for efficient bit aligned logging. [Citation Graph (, )][DBLP]


  282. Linear programming approach for performance-driven data aggregation in networks of embedded sensors. [Citation Graph (, )][DBLP]


  283. Soft error-aware design optimization of low power and time-constrained embedded systems. [Citation Graph (, )][DBLP]


  284. Contango: Integrated optimization of SoC clock networks. [Citation Graph (, )][DBLP]


  285. Clock skew optimization considering complicated power modes. [Citation Graph (, )][DBLP]


  286. A general method to make multi-clock system deterministic. [Citation Graph (, )][DBLP]


  287. Embedded software testing: What kind of problem is this? [Citation Graph (, )][DBLP]


  288. Nanoelectronics challenges for the 21st century. [Citation Graph (, )][DBLP]


  289. Cool MPSoC programming. [Citation Graph (, )][DBLP]


  290. Finding reset nondeterminism in RTL designs - scalable X-analysis methodology and case study. [Citation Graph (, )][DBLP]


  291. Optimizing equivalence checking for behavioral synthesis. [Citation Graph (, )][DBLP]


  292. Checking and deriving module paths in Verilog cell library descriptions. [Citation Graph (, )][DBLP]


  293. BACH 2 : Bounded reachability checker for compositional linear hybrid systems. [Citation Graph (, )][DBLP]


  294. DVFS based task scheduling in a harvesting WSN for Structural Health Monitoring. [Citation Graph (, )][DBLP]


  295. Power-accuracy tradeoffs in human activity transition detection. [Citation Graph (, )][DBLP]


  296. Non-invasive blood oxygen saturation monitoring for neonates using reflectance pulse oximeter. [Citation Graph (, )][DBLP]


  297. An active vision system for fall detection and posture recognition in elderly healthcare. [Citation Graph (, )][DBLP]


  298. A Smart Space application to dynamically relate medical and environmental information. [Citation Graph (, )][DBLP]


  299. An architecture for self-organization in pervasive systems. [Citation Graph (, )][DBLP]


  300. TIMBER: Time borrowing and error relaying for online timing error resilience. [Citation Graph (, )][DBLP]


  301. ERSA: Error Resilient System Architecture for probabilistic applications. [Citation Graph (, )][DBLP]


  302. Performance-asymmetry-aware topology virtualization for defect-tolerant NoC-based many-core processors. [Citation Graph (, )][DBLP]


  303. Multiplexed redundant execution: A technique for efficient fault tolerance in chip multiprocessors. [Citation Graph (, )][DBLP]


  304. Robust design of embedded systems. [Citation Graph (, )][DBLP]


  305. Energy-efficient task allocation and scheduling for multi-mode MPSoCs under lifetime reliability constraint. [Citation Graph (, )][DBLP]


  306. PM-COSYN: PE and memory co-synthesis for MPSoCs. [Citation Graph (, )][DBLP]


  307. Cost-effective slack allocation for lifetime improvement in NoC-based MPSoCs. [Citation Graph (, )][DBLP]


  308. Efficient power conversion for ultra low voltage micro scale energy transducers. [Citation Graph (, )][DBLP]


  309. Transmitting TLM transactions over analogue wire models. [Citation Graph (, )][DBLP]


  310. Intent-leveraged optimization of analog circuits via homotopy. [Citation Graph (, )][DBLP]


  311. Panel: Reliability of data centers: Hardware vs. software. [Citation Graph (, )][DBLP]


  312. Optimal regulation of traffic flows in networks-on-chip. [Citation Graph (, )][DBLP]


  313. A method to remove deadlocks in Networks-on-Chips with Wormhole flow control. [Citation Graph (, )][DBLP]


  314. An analytical method for evaluating Network-on-Chip performance. [Citation Graph (, )][DBLP]


  315. A low-area flexible MIMO detector for WiFi/WiMAX standards. [Citation Graph (, )][DBLP]


  316. An embedded wide-range and high-resolution CLOCK jitter measurement circuit. [Citation Graph (, )][DBLP]


  317. Analog circuit test based on a digital signature. [Citation Graph (, )][DBLP]


  318. DAGS: Distribution agnostic sequential Monte Carlo scheme for task execution time estimation. [Citation Graph (, )][DBLP]


  319. Taming the component timing: A CBD methodology for real-time embedded systems. [Citation Graph (, )][DBLP]


  320. Deterministic, predictable and light-weight multithreading using PRET-C. [Citation Graph (, )][DBLP]


  321. Inversed Temperature Dependence aware clock skew scheduling for sequential circuits. [Citation Graph (, )][DBLP]


  322. DynAHeal: Dynamic energy efficient task assignment for wireless healthcare systems. [Citation Graph (, )][DBLP]


  323. Instruction precomputation with memoization for fault detection. [Citation Graph (, )][DBLP]


  324. Simultaneous budget and buffer size computation for throughput-constrained task graphs. [Citation Graph (, )][DBLP]


  325. An efficient transistor-level piecewise-linear macromodeling approach for model order reduction of nonlinear circuits. [Citation Graph (, )][DBLP]


  326. Panel session - great challenges in nanoelectronics and impact on academic research: More than Moore or Beyond CMOS? [Citation Graph (, )][DBLP]


  327. 3D-integration of silicon devices: A key technology for sophisticated products. [Citation Graph (, )][DBLP]


  328. Creating 3D specific systems: Architecture, design and CAD. [Citation Graph (, )][DBLP]


  329. Testing TSV-based three-dimensional stacked ICs. [Citation Graph (, )][DBLP]


  330. Leveraging dominators for preprocessing QBF. [Citation Graph (, )][DBLP]


  331. Formal specification of networks-on-chips: deadlock and evacuation. [Citation Graph (, )][DBLP]


  332. Tighter integration of BDDs and SMT for Predicate Abstraction. [Citation Graph (, )][DBLP]


  333. An HVS-based Adaptive Computational Complexity Reduction Scheme for H.264/AVC video encoder using Prognostic Early Mode Exclusion. [Citation Graph (, )][DBLP]


  334. Scheduling and energy-distortion tradeoffs with operational refinement of image processing. [Citation Graph (, )][DBLP]


  335. enBudget: A Run-Time Adaptive Predictive Energy-Budgeting scheme for energy-aware Motion Estimation in H.264/MPEG-4 AVC video encoder. [Citation Graph (, )][DBLP]


  336. A method for design of impulse bursts noise filters optimized for FPGA implementations. [Citation Graph (, )][DBLP]


  337. Exploration of hardware sharing for image encoders. [Citation Graph (, )][DBLP]


  338. Towards hardware stereoscopic 3D reconstruction a real-time FPGA computation of the disparity map. [Citation Graph (, )][DBLP]


  339. A robust ADC code hit counting technique. [Citation Graph (, )][DBLP]


  340. An automatic test generation framework for digitally-assisted adaptive equalizers in high-speed serial links. [Citation Graph (, )][DBLP]


  341. Fault diagnosis of analog circuits based on machine learning. [Citation Graph (, )][DBLP]


  342. Block-level bayesian diagnosis of analogue electronic circuits. [Citation Graph (, )][DBLP]


  343. Control network generator for latency insensitive designs. [Citation Graph (, )][DBLP]


  344. Using Speculative Functional Units in high level synthesis. [Citation Graph (, )][DBLP]


  345. Retiming multi-rate DSP algorithms to meet real-time requirement. [Citation Graph (, )][DBLP]


  346. Combining optimizations in automated low power design. [Citation Graph (, )][DBLP]


  347. A new quaternary FPGA based on a voltage-mode multi-valued circuit. [Citation Graph (, )][DBLP]


  348. An evaluation of a slice fault aware tool chain. [Citation Graph (, )][DBLP]


  349. Reliability- and process variation-aware placement for FPGAs. [Citation Graph (, )][DBLP]

NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002