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Conferences in DBLP

2008 (conf/ddecs/2008)

  1. The Guiding Light for Chip Testing. [Citation Graph (, )][DBLP]

  2. The Wall Ahead is Made of Rubber. [Citation Graph (, )][DBLP]

  3. The Quest for Test: Will Redundancy Cover All? [Citation Graph (, )][DBLP]

  4. Deep-Submicron MOS Transistor Matching: A Case Study. [Citation Graph (, )][DBLP]

  5. Three Subthreshold Flip-Flop Cells Characterized in 90 nm and 65 nm CMOS Technology. [Citation Graph (, )][DBLP]

  6. Improving Circuit Security against Power Analysis Attacks with Subthreshold Operation. [Citation Graph (, )][DBLP]

  7. Controllable Local Clock Signal Generator for Deep Submicron GALS Architectures. [Citation Graph (, )][DBLP]

  8. Computation of a nonlinear squashing function in digital neural networks. [Citation Graph (, )][DBLP]

  9. An Integrated Input Encoding and Symbolic Functional Decomposition for LUT-Based FPGAs. [Citation Graph (, )][DBLP]

  10. Portable Measurement Equipment for Continuous Biomedical Monitoring using Microelectrodes. [Citation Graph (, )][DBLP]

  11. Design of Erasure Codes for Digital Multimedia Transmitting. [Citation Graph (, )][DBLP]

  12. Process Tolerant Design Using Thermal and Power-Supply Tolerance in Pipeline Based Circuits. [Citation Graph (, )][DBLP]

  13. A Resistorless Voltage Reference Source for 90 nm CMOS Technology with Low Sensitivity to Process and Temperature Variations. [Citation Graph (, )][DBLP]

  14. Temperature-Aware Task Mapping for Energy Optimization with Dynamic Voltage Scaling. [Citation Graph (, )][DBLP]

  15. Gain reduction by gate-leakage currents in regulated cascodes. [Citation Graph (, )][DBLP]

  16. A Trapezoidal Approach to Corner Stitching Data Structures for Arbitrary Routing Angles. [Citation Graph (, )][DBLP]

  17. Continuous-Time Common-Mode Feedback Circuit for Applications with Large Output Swing and High Output Impedance. [Citation Graph (, )][DBLP]

  18. A Spread-Spectrum Clock Generator Using Fractional PLL Controlled Delta-Sigma Modulator for Serial-ATA III. [Citation Graph (, )][DBLP]

  19. Incremental SAT Instance Generation for SAT-based ATPG. [Citation Graph (, )][DBLP]

  20. Concurrent Error Detection for Combinational Logic Blocks Implemented with Embedded Memory Blocks of FPGAs. [Citation Graph (, )][DBLP]

  21. Analysis of the influence of intermittent faults in a microcontroller. [Citation Graph (, )][DBLP]

  22. Mapping of 40 MHz MIMO SDM-OFDM Baseband Processing on Multi-Processor SDR Platform. [Citation Graph (, )][DBLP]

  23. Cluster-based Simulated Annealing for Mapping Cores onto 2D Mesh Networks on Chip. [Citation Graph (, )][DBLP]

  24. MPEG-based Performance Comparison between Network-on-Chip and AMBA MPSoC. [Citation Graph (, )][DBLP]

  25. Rapid Prototyping of NoC Architectures from a SystemC Specification. [Citation Graph (, )][DBLP]

  26. Novel Hardware Implementation of Adaptive Median Filters. [Citation Graph (, )][DBLP]

  27. A New Design Technique for Weakly Indicating Function Blocks. [Citation Graph (, )][DBLP]

  28. Fast Boolean Minimizer for Completely Specified Functions. [Citation Graph (, )][DBLP]

  29. The HDL and FE Thermal Modeling of Heterogeneous Systems. [Citation Graph (, )][DBLP]

  30. A System-On-Chip for Wireless Body Area Sensor Network Node. [Citation Graph (, )][DBLP]

  31. Mixed-Signal DFT for fully testable ASIC. [Citation Graph (, )][DBLP]

  32. On Minimizing RTOS Aperiodic Tasks Server Energy Consumption. [Citation Graph (, )][DBLP]

  33. Boolean Formalisation of the PMC Model for Faulty Units Diagnosis in Regular Multi-Processor Systems. [Citation Graph (, )][DBLP]

  34. A Dual-Threaded Architecture for Interval Arithmetic Coprocessor with Shared Floating Point Units. [Citation Graph (, )][DBLP]

  35. Design of Time-to-Digital Converter Output Interface. [Citation Graph (, )][DBLP]

  36. Design and Simulation of Runtime Reconfigurable Systems. [Citation Graph (, )][DBLP]

  37. Modeling and observing the jitter in ring oscillators implemented in FPGAs. [Citation Graph (, )][DBLP]

  38. Cryptographic System on a Chip based on Actel ARM7 Soft-Core with Embedded True Random Number Generator. [Citation Graph (, )][DBLP]

  39. Various MDCT implementations in 0.35µm CMOS. [Citation Graph (, )][DBLP]

  40. Low-Voltage Low-Power Highly Linear Down-Sampling Mixer in 65nm Digital CMOS Technology. [Citation Graph (, )][DBLP]

  41. Analysis of Applicability of Partial Runtime Reconfiguration in Fault Emulator in Xilinx FPGAs. [Citation Graph (, )][DBLP]

  42. Implementation of Dynamically Reconfigurable Test Architecture for FPGA Circuits. [Citation Graph (, )][DBLP]

  43. A Partial Scan Based Test Generation for Asynchronous Circuits. [Citation Graph (, )][DBLP]

  44. Efficient Allocation of Verification Resources using Revision History Information. [Citation Graph (, )][DBLP]

  45. Ad-Hoc Translations to Close Verilog Semantics Gap. [Citation Graph (, )][DBLP]

  46. Code Coverage Analysis using High-Level Decision Diagrams. [Citation Graph (, )][DBLP]

  47. Probabilistic Model Checking and Reliability of Results. [Citation Graph (, )][DBLP]

  48. Network Probe for Flexible Flow Monitoring. [Citation Graph (, )][DBLP]

  49. NetCOPE: Platform for Rapid Development of Network Applications. [Citation Graph (, )][DBLP]

  50. IP-based Systematic Design of Power-and Matching-limited Circuits. [Citation Graph (, )][DBLP]

  51. A Low Leakage Non-Volatile Memory Voltage Pulse Generator for RFID Applications. [Citation Graph (, )][DBLP]

  52. Calculating the fault coverage for dual neighboring faults using single stuck-at fault patterns. [Citation Graph (, )][DBLP]

  53. Evaluation of the Iddq Signature in devices with Gauss-distributed background current. [Citation Graph (, )][DBLP]

  54. Interconnect Faults Identification and Localization Using Modified Ring LFSRs. [Citation Graph (, )][DBLP]

  55. Testing an Emergency Luminaire Circuit Using a Fault Dictionary Approach. [Citation Graph (, )][DBLP]

  56. Reduction of Test Vectors Volume by Means of Gate-Level Reconfiguration. [Citation Graph (, )][DBLP]

  57. Built-In Current Monitor for IDDQ Testing in CMOS 90 nm Technology. [Citation Graph (, )][DBLP]

  58. Diagnosis of Realistic Defects Based on the X-Fault Model. [Citation Graph (, )][DBLP]

  59. Improving Fault Tolerance by Using Reconfigurable Asynchronous Circuits. [Citation Graph (, )][DBLP]

  60. Web-Based Framework for Parallel Distributed Test. [Citation Graph (, )][DBLP]

  61. Calculation of LFSR Seed and Polynomial Pair for BIST Applications. [Citation Graph (, )][DBLP]

  62. Excitation optimization in fault diagnosis of analog electronic circuits. [Citation Graph (, )][DBLP]

  63. Virtual Testing Environment for A/D Converters in Verilog-A and Maple Platform. [Citation Graph (, )][DBLP]

  64. Efficient Estimation of Die-Level Process Parameter Variations via the EM-Algorithm. [Citation Graph (, )][DBLP]

  65. Experimental Analog Circuit for Parametric Test Methods Efficiency Evaluation. [Citation Graph (, )][DBLP]

  66. The Influence of Global Parametric Faults on Analogue Electronic Circuits Time Domain Response Features. [Citation Graph (, )][DBLP]

  67. A novel method for test and calibration of capacitive accelerometers with a fully electrical setup. [Citation Graph (, )][DBLP]

  68. On-chip Integration of Magnetic Force Sensing Current Monitors. [Citation Graph (, )][DBLP]

  69. A Cost Effective BIST Second-Order Sigma-Delta-Modulator. [Citation Graph (, )][DBLP]

  70. SoC Symbolic Simulation: a case study on delay fault testing. [Citation Graph (, )][DBLP]

  71. SoCECT: System on Chip Embedded Core Test. [Citation Graph (, )][DBLP]

  72. Optimal Backgrounds Selection for Multi Run Memory Testing. [Citation Graph (, )][DBLP]

  73. Software-Based Self-Test Strategy for Data Cache Memories Embedded in SoCs. [Citation Graph (, )][DBLP]

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for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002