Conferences in DBLP
A Design of 14-bits ADC and DAC for CODEC Applications in 0.18 µm CMOS Process. [Citation Graph (, )][DBLP ] Compensation-Capacitor Free Pseudo Three-Stage Amplifier with Large Capacitive Loads. [Citation Graph (, )][DBLP ] The Design and Optimization of a 25 kS/s 10 bit Micropower Current S/H Cell for Weak Current Bio-medical Applications. [Citation Graph (, )][DBLP ] A Single-Stage SEPIC PFC Converter for Multiple Lighting LED Lamps. [Citation Graph (, )][DBLP ] Using Genetic Evolutionary Software Application Testing to Verify a DSP SoC. [Citation Graph (, )][DBLP ] Channel Width Utilization Improvement in Testing NoC-Based Systems for Test Time Reduction. [Citation Graph (, )][DBLP ] Coordinated versus Uncoordinated Checkpoint Recovery for Network-on-Chip Based Systems. [Citation Graph (, )][DBLP ] Testing of a Highly Reconfigurable Processor Core for Dependable Data Streaming Applications. [Citation Graph (, )][DBLP ] A Fast Algorithm for the Chirp Rate Estimation. [Citation Graph (, )][DBLP ] Crack Detection on Asphalt Surface Image Using Enhanced Grid Cell Analysis. [Citation Graph (, )][DBLP ] Interpolation Models for Image Super-resolution. [Citation Graph (, )][DBLP ] Performance Analysis of a Vehicle Crash Control System using Image. [Citation Graph (, )][DBLP ] A High Speed CMOS Transmitter and Rail-to-Rail Receiver. [Citation Graph (, )][DBLP ] Design of a 12-Channel 120-Gbs Optical Receiver Array in 0.18-µm CMOS Technology. [Citation Graph (, )][DBLP ] 99-dB High-Performance Delta-Sigma Modulator for 20-kHz Bandwidth. [Citation Graph (, )][DBLP ] Analysis and Design of a Continuous-Time Sigma-Delta Modulator with 20 MHz Signal Bandwidth, 53.6 dB Dynamic Range and 51.4 dB SNDR. [Citation Graph (, )][DBLP ] An FPGA Implementation of the Searcher Algorithm. [Citation Graph (, )][DBLP ] Analysis of CPU Utilisation and Stack Consumption of a Multimedia Embedded System. [Citation Graph (, )][DBLP ] Research on System Usability of Digital Libraries in China. [Citation Graph (, )][DBLP ] A Fast Two-Stage Sample-and-Hold Amplifier for Pipelined ADC Application. [Citation Graph (, )][DBLP ] Low Phase Noise Bond Wire VCO for DVB-H. [Citation Graph (, )][DBLP ] A Novel Dummy Bitline Driver for Read Margin Improvement in an eSRAM. [Citation Graph (, )][DBLP ] A 14-bit 320 MSPS Segmented Current-Steering D/A Converter for High-Speed Applications. [Citation Graph (, )][DBLP ] A Multiprocessor System for a Small Size Soccer Robot Control System. [Citation Graph (, )][DBLP ] Low Cost Arbitration Method for Arbitrarily Scalable Multiprocessor Systems. [Citation Graph (, )][DBLP ] An Efficient Design of Single Event Transients Tolerance for Logic Circuits. [Citation Graph (, )][DBLP ] Adaptive Diagnostic Pattern Generation for Scan Chains. [Citation Graph (, )][DBLP ] Built-In Self-Test for Embedded Voltage Regulator. [Citation Graph (, )][DBLP ] Recent Trends in FPGA Architectures and Applications. [Citation Graph (, )][DBLP ] Embedding Smart Buffers for Window Operations in a Stream-Oriented C-to-VHDL Compiler. [Citation Graph (, )][DBLP ] Implementation of Hardware Encryption Engine for Wireless Communication on a Reconfigurable Instruction Cell Architecture. [Citation Graph (, )][DBLP ] Dynamic Slowdown and Partial Reconfiguration to Optimize Energy in FPGA Based Auto-adaptive SoPC. [Citation Graph (, )][DBLP ] xDSL Network Upgrade Employing FPGAs. [Citation Graph (, )][DBLP ] Power Issues on Circuit Design for Cochlear Implants. [Citation Graph (, )][DBLP ] Architecture of a Low Storage Digital Pixel Sensor Array with an On-Line Block-Based Compression. [Citation Graph (, )][DBLP ] Effects of Insulator Thickness on the Sensing Properties of MISiC Schottky-Diode Hydrogen Sensor. [Citation Graph (, )][DBLP ] High Speed Depth Estimation Using Tilted Focal Planes. [Citation Graph (, )][DBLP ] Multi-Phase Charge Pump Generating Positive and Negative High Voltages for TFT-LCD Gate Driving. [Citation Graph (, )][DBLP ] Dynamic Co-operative Intelligent Memory. [Citation Graph (, )][DBLP ] An Accurate and Energy-Efficient Way Determination Technique for Instruction Caches by Early Tab Matching. [Citation Graph (, )][DBLP ] Proposal for a Bidirectional Gate Using Pseudo Floating-Gate. [Citation Graph (, )][DBLP ] Read Stability and Write Ability Tradeoff for 6T SRAM Cells in Double-Gate CMOS. [Citation Graph (, )][DBLP ] Compact Models for Signal Transient and Crosstalk Noise of Coupled RLC Interconnect Lines with Ramp Inputs. [Citation Graph (, )][DBLP ] Improving Diagnosis Resolution without Physical Information. [Citation Graph (, )][DBLP ] Predictive Die-Level Reliability-Yield Modeling for Deep Sub-micron Devices. [Citation Graph (, )][DBLP ] Hierarchical Calculation of Malicious Faults for Evaluating the Fault-Tolerance. [Citation Graph (, )][DBLP ] FPGA implementation of a Single Pass Connected Components Algorithm. [Citation Graph (, )][DBLP ] A Low Voltage Rail-to-Rail OPAMP Design for Biomedical Signal Filtering Applications. [Citation Graph (, )][DBLP ] Workload-Based Dynamic Voltage Scaling with the QoS for Streaming Video. [Citation Graph (, )][DBLP ] Speech Recognition of Isolated Malayalam Words Using Wavelet Features and Artificial Neural Network. [Citation Graph (, )][DBLP ] FPGA Based Real Time Solution for Sensitivity Time Control. [Citation Graph (, )][DBLP ] A Jittered-Sampling Correction Technique for ADCs. [Citation Graph (, )][DBLP ] Robust JPEG2000 Image Transmission over IEEE 802.15.4. [Citation Graph (, )][DBLP ] New D-Type Flip-Flop Design Using Negative Differential Resistance Circuits. [Citation Graph (, )][DBLP ] Experimental Characterisations of Coupled Transmission Lines. [Citation Graph (, )][DBLP ] A Low Power Deterministic Test Pattern Generator for BIST Based on Cellular Automata. [Citation Graph (, )][DBLP ] A Test Data Compression Method for System-on-a-Chip. [Citation Graph (, )][DBLP ] A Hybrid of Clonal Selection Algorithm and Frequency Sampling Method for Designing a 2-D FIR Filter. [Citation Graph (, )][DBLP ] A Generation Flow for Self-Reconfiguration Controllers Customization. [Citation Graph (, )][DBLP ] Design of High-Speed Floating Point Multiplier. [Citation Graph (, )][DBLP ] High Performance Elliptic Curve Cryptographic Processor Over GF(2^163). [Citation Graph (, )][DBLP ] A Visual Notation for Processor and Resource Scheduling. [Citation Graph (, )][DBLP ] Design for Testability of Functional Cores in High Performance Node Architectures. [Citation Graph (, )][DBLP ] Test Response Data Volume and Wire Length Reductions for Extended Compatibilities Scan Tree Construction. [Citation Graph (, )][DBLP ] AES-Based BIST: Self-Test, Test Pattern Generation and Signature Analysis. [Citation Graph (, )][DBLP ] Oscillation-Based Test in Data Converters: On-Line Monitoring. [Citation Graph (, )][DBLP ] A Case Study on At-Speed Testing for a Gigahertz Microprocessor. [Citation Graph (, )][DBLP ] A Charge Pump Circuit - Cascading High-Voltage Clock Generator. [Citation Graph (, )][DBLP ] Threshold Voltage Start-up Boost Converter for Sub-mA Applications. [Citation Graph (, )][DBLP ] Design of a Low-Voltage CMOS Charge Pump. [Citation Graph (, )][DBLP ] High-Input Impedance Voltage-Mode Universal Biquadratic Filter with One input and Five Outputs Using DDCCs. [Citation Graph (, )][DBLP ] Temporal-Spatial Correlation Based Mode Decision Algorithm for H.264/AVC Encoder. [Citation Graph (, )][DBLP ] A Software-to-Hardware Self-Mapping Technique to Enhance Program Throughput for Portable Multimedia Workloads. [Citation Graph (, )][DBLP ] Improved Policies for Drowsy Caches in Embedded Processors. [Citation Graph (, )][DBLP ] Improving Cost-Effectiveness Using a Micro-level Static Architecture for Stream Applications. [Citation Graph (, )][DBLP ] A Compact CMOS Face Detection Architecture Based on Shunting Inhibitory Convolutional Neural Networks. [Citation Graph (, )][DBLP ] Temperature Modulation for Tin-Oxide Gas Sensors. [Citation Graph (, )][DBLP ] Eigenspectra Palmprint Recognition. [Citation Graph (, )][DBLP ] VLSI Architecture and FPGA Implementation of a Hybrid Message-Embedded Self-Synchronizing Stream Cipher. [Citation Graph (, )][DBLP ] DWT/PCA Face Recognition using Automatic Coefficient Selection. [Citation Graph (, )][DBLP ] A Spiking Neural Network for Gas Discrimination Using a Tin Oxide Sensor Array. [Citation Graph (, )][DBLP ] A Hybrid Interconnect Network-on-Chip and a Transaction Level Modeling Approach for Reconfigurable Computing. [Citation Graph (, )][DBLP ] A Requirements-Driven Reconfigurable SoC Communication Infrastructure Design Flow. [Citation Graph (, )][DBLP ] High-Speed Priority Queue Architecture for Multiple Out Links. [Citation Graph (, )][DBLP ] Integrated Mapping and Scheduling for Circuit-Switched Network-on-Chip Architectures. [Citation Graph (, )][DBLP ] Drift Invariant Gas Recognition Technique for On Chip Tin Oxide Gas Sensor Array. [Citation Graph (, )][DBLP ] On Using Fingerprint-Sensors for PIN-Pad Entry. [Citation Graph (, )][DBLP ] FPGA Implementation of a Predictive Vector Quantization Image Compression Algorithm for Image Sensor Applications. [Citation Graph (, )][DBLP ] Integrating Dynamic Load Balancing Strategies into the Car-Network. [Citation Graph (, )][DBLP ] A Design of the Frequency Synthesizer for UWB Application in 0.13 µm RF CMOS Process. [Citation Graph (, )][DBLP ] Analog to Digital Converter Specification for UMTS/FDD Receiver Applications. [Citation Graph (, )][DBLP ] A Design Workflow for the Identification of Area Constraints in Dynamic Reconfigurable Systems. [Citation Graph (, )][DBLP ] Bus Binding, Re-ordering, and Encoding for Crosstalk-Producing Switching Activity Minimization during High Level Synthesis. [Citation Graph (, )][DBLP ] Scalable Montgomery Multiplier for Finite Fields GF(p) and GF(2^m). [Citation Graph (, )][DBLP ] Static Crosstalk Noise Analysis with Transition Map. [Citation Graph (, )][DBLP ] Implementation of the Embedded System for Visually-Impaired People. [Citation Graph (, )][DBLP ] Model-Based Gaze Direction Estimation in Office Environment. [Citation Graph (, )][DBLP ] Fast Evaluation of the Square Root and Other Nonlinear Functions in FPGA. [Citation Graph (, )][DBLP ] Configurable Blocks for Multi-precision Multiplication. [Citation Graph (, )][DBLP ] High Performance FPGA Implementation of the Mersenne Twister. [Citation Graph (, )][DBLP ] Addressing Heterogeneous Bandwidth Requirements in Modified Fat-Tree Networks-on-Chips. [Citation Graph (, )][DBLP ] The Fourier Spectrum Analysis of Optical Feedback Self-Mixing Signal under Weak and Moderate Feedback. [Citation Graph (, )][DBLP ] Elimination of Gamma Non-linear Luminance Effects for Digital Video Projection Phase Measuring Profilometers. [Citation Graph (, )][DBLP ] Integrated CMOS Analog Neural Network Ability to Linearize the Distorted Characteristic of HPA Embedded in Satellites. [Citation Graph (, )][DBLP ] Compact Gray-Code Counter/Memory Circuits for Spiking Pixels. [Citation Graph (, )][DBLP ] Calibration and Debugging of Multi-step Analog to Digital Converters. [Citation Graph (, )][DBLP ] A Prevenient Voltage Stress Test Method for High Density Memory. [Citation Graph (, )][DBLP ] A Scan-Based Delay Test Method for Reduction of Overtesting. [Citation Graph (, )][DBLP ] An Integrated Validation Environment for Differential Power Analysis. [Citation Graph (, )][DBLP ] Automated Testing of FlexRay Clusters for System Inconsistencies in Automotive Networks. [Citation Graph (, )][DBLP ] Early Design Phase Power Performance Trade-Offs Using In-Situ Macro Models. [Citation Graph (, )][DBLP ] Low Voltage Design against Power Analysis Attacks. [Citation Graph (, )][DBLP ] Electrical Power Monitoring System Using Thermochron Sensor and 1-Wire Communication Protocol. [Citation Graph (, )][DBLP ] Efficient VLSI Layout of Edge Product Networks. [Citation Graph (, )][DBLP ] Towards a Petri Net Based Approach to Model and Synthesise Dynamic Reconfiguration for FPGAs. [Citation Graph (, )][DBLP ] Arbitrary Waveform Generator Based on Direct Digital Frequency Synthesizer. [Citation Graph (, )][DBLP ] Design of a Data Concentrator Card for the Readout of the Compact Muon Solenoid Electromagnetic Calorimeter. [Citation Graph (, )][DBLP ] A Novel Approach to High-Level Property Checking Using Wu's Method. [Citation Graph (, )][DBLP ] Test Set Stripping Limiting the Maximum Number of Specified Bits. [Citation Graph (, )][DBLP ] An Automated Fault Injection Technique Based on VHDL Syntax Analysis and Stratified Sampling. [Citation Graph (, )][DBLP ] CreaTe: A New Programme to Attract Engineers as Design Artists. [Citation Graph (, )][DBLP ] High-Performance Pseudorandom Number Generator Using Two-Dimensional Cellular Automata. [Citation Graph (, )][DBLP ] Design Automation of UHF RFID Tag Antenna Design Using a Genetic Algorithm Linked to MWS CST. [Citation Graph (, )][DBLP ]