The SCEAS System
Navigation Menu

Conferences in DBLP

Workshop on Electronic Design, Test and Applications (delta)
2008 (conf/delta/2008)


  1. A Design of 14-bits ADC and DAC for CODEC Applications in 0.18 µm CMOS Process. [Citation Graph (, )][DBLP]


  2. Compensation-Capacitor Free Pseudo Three-Stage Amplifier with Large Capacitive Loads. [Citation Graph (, )][DBLP]


  3. The Design and Optimization of a 25 kS/s 10 bit Micropower Current S/H Cell for Weak Current Bio-medical Applications. [Citation Graph (, )][DBLP]


  4. A Single-Stage SEPIC PFC Converter for Multiple Lighting LED Lamps. [Citation Graph (, )][DBLP]


  5. Using Genetic Evolutionary Software Application Testing to Verify a DSP SoC. [Citation Graph (, )][DBLP]


  6. Channel Width Utilization Improvement in Testing NoC-Based Systems for Test Time Reduction. [Citation Graph (, )][DBLP]


  7. Coordinated versus Uncoordinated Checkpoint Recovery for Network-on-Chip Based Systems. [Citation Graph (, )][DBLP]


  8. Testing of a Highly Reconfigurable Processor Core for Dependable Data Streaming Applications. [Citation Graph (, )][DBLP]


  9. A Fast Algorithm for the Chirp Rate Estimation. [Citation Graph (, )][DBLP]


  10. Crack Detection on Asphalt Surface Image Using Enhanced Grid Cell Analysis. [Citation Graph (, )][DBLP]


  11. Interpolation Models for Image Super-resolution. [Citation Graph (, )][DBLP]


  12. Performance Analysis of a Vehicle Crash Control System using Image. [Citation Graph (, )][DBLP]


  13. A High Speed CMOS Transmitter and Rail-to-Rail Receiver. [Citation Graph (, )][DBLP]


  14. Design of a 12-Channel 120-Gbs Optical Receiver Array in 0.18-µm CMOS Technology. [Citation Graph (, )][DBLP]


  15. 99-dB High-Performance Delta-Sigma Modulator for 20-kHz Bandwidth. [Citation Graph (, )][DBLP]


  16. Analysis and Design of a Continuous-Time Sigma-Delta Modulator with 20 MHz Signal Bandwidth, 53.6 dB Dynamic Range and 51.4 dB SNDR. [Citation Graph (, )][DBLP]


  17. An FPGA Implementation of the Searcher Algorithm. [Citation Graph (, )][DBLP]


  18. Analysis of CPU Utilisation and Stack Consumption of a Multimedia Embedded System. [Citation Graph (, )][DBLP]


  19. Research on System Usability of Digital Libraries in China. [Citation Graph (, )][DBLP]


  20. A Fast Two-Stage Sample-and-Hold Amplifier for Pipelined ADC Application. [Citation Graph (, )][DBLP]


  21. Low Phase Noise Bond Wire VCO for DVB-H. [Citation Graph (, )][DBLP]


  22. A Novel Dummy Bitline Driver for Read Margin Improvement in an eSRAM. [Citation Graph (, )][DBLP]


  23. A 14-bit 320 MSPS Segmented Current-Steering D/A Converter for High-Speed Applications. [Citation Graph (, )][DBLP]


  24. A Multiprocessor System for a Small Size Soccer Robot Control System. [Citation Graph (, )][DBLP]


  25. Low Cost Arbitration Method for Arbitrarily Scalable Multiprocessor Systems. [Citation Graph (, )][DBLP]


  26. An Efficient Design of Single Event Transients Tolerance for Logic Circuits. [Citation Graph (, )][DBLP]


  27. Adaptive Diagnostic Pattern Generation for Scan Chains. [Citation Graph (, )][DBLP]


  28. Built-In Self-Test for Embedded Voltage Regulator. [Citation Graph (, )][DBLP]


  29. Recent Trends in FPGA Architectures and Applications. [Citation Graph (, )][DBLP]


  30. Embedding Smart Buffers for Window Operations in a Stream-Oriented C-to-VHDL Compiler. [Citation Graph (, )][DBLP]


  31. Implementation of Hardware Encryption Engine for Wireless Communication on a Reconfigurable Instruction Cell Architecture. [Citation Graph (, )][DBLP]


  32. Dynamic Slowdown and Partial Reconfiguration to Optimize Energy in FPGA Based Auto-adaptive SoPC. [Citation Graph (, )][DBLP]


  33. xDSL Network Upgrade Employing FPGAs. [Citation Graph (, )][DBLP]


  34. Power Issues on Circuit Design for Cochlear Implants. [Citation Graph (, )][DBLP]


  35. Architecture of a Low Storage Digital Pixel Sensor Array with an On-Line Block-Based Compression. [Citation Graph (, )][DBLP]


  36. Effects of Insulator Thickness on the Sensing Properties of MISiC Schottky-Diode Hydrogen Sensor. [Citation Graph (, )][DBLP]


  37. High Speed Depth Estimation Using Tilted Focal Planes. [Citation Graph (, )][DBLP]


  38. Multi-Phase Charge Pump Generating Positive and Negative High Voltages for TFT-LCD Gate Driving. [Citation Graph (, )][DBLP]


  39. Dynamic Co-operative Intelligent Memory. [Citation Graph (, )][DBLP]


  40. An Accurate and Energy-Efficient Way Determination Technique for Instruction Caches by Early Tab Matching. [Citation Graph (, )][DBLP]


  41. Proposal for a Bidirectional Gate Using Pseudo Floating-Gate. [Citation Graph (, )][DBLP]


  42. Read Stability and Write Ability Tradeoff for 6T SRAM Cells in Double-Gate CMOS. [Citation Graph (, )][DBLP]


  43. Compact Models for Signal Transient and Crosstalk Noise of Coupled RLC Interconnect Lines with Ramp Inputs. [Citation Graph (, )][DBLP]


  44. Improving Diagnosis Resolution without Physical Information. [Citation Graph (, )][DBLP]


  45. Predictive Die-Level Reliability-Yield Modeling for Deep Sub-micron Devices. [Citation Graph (, )][DBLP]


  46. Hierarchical Calculation of Malicious Faults for Evaluating the Fault-Tolerance. [Citation Graph (, )][DBLP]


  47. FPGA implementation of a Single Pass Connected Components Algorithm. [Citation Graph (, )][DBLP]


  48. A Low Voltage Rail-to-Rail OPAMP Design for Biomedical Signal Filtering Applications. [Citation Graph (, )][DBLP]


  49. Workload-Based Dynamic Voltage Scaling with the QoS for Streaming Video. [Citation Graph (, )][DBLP]


  50. Speech Recognition of Isolated Malayalam Words Using Wavelet Features and Artificial Neural Network. [Citation Graph (, )][DBLP]


  51. FPGA Based Real Time Solution for Sensitivity Time Control. [Citation Graph (, )][DBLP]


  52. A Jittered-Sampling Correction Technique for ADCs. [Citation Graph (, )][DBLP]


  53. Robust JPEG2000 Image Transmission over IEEE 802.15.4. [Citation Graph (, )][DBLP]


  54. New D-Type Flip-Flop Design Using Negative Differential Resistance Circuits. [Citation Graph (, )][DBLP]


  55. Experimental Characterisations of Coupled Transmission Lines. [Citation Graph (, )][DBLP]


  56. A Low Power Deterministic Test Pattern Generator for BIST Based on Cellular Automata. [Citation Graph (, )][DBLP]


  57. A Test Data Compression Method for System-on-a-Chip. [Citation Graph (, )][DBLP]


  58. A Hybrid of Clonal Selection Algorithm and Frequency Sampling Method for Designing a 2-D FIR Filter. [Citation Graph (, )][DBLP]


  59. A Generation Flow for Self-Reconfiguration Controllers Customization. [Citation Graph (, )][DBLP]


  60. Design of High-Speed Floating Point Multiplier. [Citation Graph (, )][DBLP]


  61. High Performance Elliptic Curve Cryptographic Processor Over GF(2^163). [Citation Graph (, )][DBLP]


  62. A Visual Notation for Processor and Resource Scheduling. [Citation Graph (, )][DBLP]


  63. Design for Testability of Functional Cores in High Performance Node Architectures. [Citation Graph (, )][DBLP]


  64. Test Response Data Volume and Wire Length Reductions for Extended Compatibilities Scan Tree Construction. [Citation Graph (, )][DBLP]


  65. AES-Based BIST: Self-Test, Test Pattern Generation and Signature Analysis. [Citation Graph (, )][DBLP]


  66. Oscillation-Based Test in Data Converters: On-Line Monitoring. [Citation Graph (, )][DBLP]


  67. A Case Study on At-Speed Testing for a Gigahertz Microprocessor. [Citation Graph (, )][DBLP]


  68. A Charge Pump Circuit - Cascading High-Voltage Clock Generator. [Citation Graph (, )][DBLP]


  69. Threshold Voltage Start-up Boost Converter for Sub-mA Applications. [Citation Graph (, )][DBLP]


  70. Design of a Low-Voltage CMOS Charge Pump. [Citation Graph (, )][DBLP]


  71. High-Input Impedance Voltage-Mode Universal Biquadratic Filter with One input and Five Outputs Using DDCCs. [Citation Graph (, )][DBLP]


  72. Temporal-Spatial Correlation Based Mode Decision Algorithm for H.264/AVC Encoder. [Citation Graph (, )][DBLP]


  73. A Software-to-Hardware Self-Mapping Technique to Enhance Program Throughput for Portable Multimedia Workloads. [Citation Graph (, )][DBLP]


  74. Improved Policies for Drowsy Caches in Embedded Processors. [Citation Graph (, )][DBLP]


  75. Improving Cost-Effectiveness Using a Micro-level Static Architecture for Stream Applications. [Citation Graph (, )][DBLP]


  76. A Compact CMOS Face Detection Architecture Based on Shunting Inhibitory Convolutional Neural Networks. [Citation Graph (, )][DBLP]


  77. Temperature Modulation for Tin-Oxide Gas Sensors. [Citation Graph (, )][DBLP]


  78. Eigenspectra Palmprint Recognition. [Citation Graph (, )][DBLP]


  79. VLSI Architecture and FPGA Implementation of a Hybrid Message-Embedded Self-Synchronizing Stream Cipher. [Citation Graph (, )][DBLP]


  80. DWT/PCA Face Recognition using Automatic Coefficient Selection. [Citation Graph (, )][DBLP]


  81. A Spiking Neural Network for Gas Discrimination Using a Tin Oxide Sensor Array. [Citation Graph (, )][DBLP]


  82. A Hybrid Interconnect Network-on-Chip and a Transaction Level Modeling Approach for Reconfigurable Computing. [Citation Graph (, )][DBLP]


  83. A Requirements-Driven Reconfigurable SoC Communication Infrastructure Design Flow. [Citation Graph (, )][DBLP]


  84. High-Speed Priority Queue Architecture for Multiple Out Links. [Citation Graph (, )][DBLP]


  85. Integrated Mapping and Scheduling for Circuit-Switched Network-on-Chip Architectures. [Citation Graph (, )][DBLP]


  86. Drift Invariant Gas Recognition Technique for On Chip Tin Oxide Gas Sensor Array. [Citation Graph (, )][DBLP]


  87. On Using Fingerprint-Sensors for PIN-Pad Entry. [Citation Graph (, )][DBLP]


  88. FPGA Implementation of a Predictive Vector Quantization Image Compression Algorithm for Image Sensor Applications. [Citation Graph (, )][DBLP]


  89. Integrating Dynamic Load Balancing Strategies into the Car-Network. [Citation Graph (, )][DBLP]


  90. A Design of the Frequency Synthesizer for UWB Application in 0.13 µm RF CMOS Process. [Citation Graph (, )][DBLP]


  91. Analog to Digital Converter Specification for UMTS/FDD Receiver Applications. [Citation Graph (, )][DBLP]


  92. A Design Workflow for the Identification of Area Constraints in Dynamic Reconfigurable Systems. [Citation Graph (, )][DBLP]


  93. Bus Binding, Re-ordering, and Encoding for Crosstalk-Producing Switching Activity Minimization during High Level Synthesis. [Citation Graph (, )][DBLP]


  94. Scalable Montgomery Multiplier for Finite Fields GF(p) and GF(2^m). [Citation Graph (, )][DBLP]


  95. Static Crosstalk Noise Analysis with Transition Map. [Citation Graph (, )][DBLP]


  96. Implementation of the Embedded System for Visually-Impaired People. [Citation Graph (, )][DBLP]


  97. Model-Based Gaze Direction Estimation in Office Environment. [Citation Graph (, )][DBLP]


  98. Fast Evaluation of the Square Root and Other Nonlinear Functions in FPGA. [Citation Graph (, )][DBLP]


  99. Configurable Blocks for Multi-precision Multiplication. [Citation Graph (, )][DBLP]


  100. High Performance FPGA Implementation of the Mersenne Twister. [Citation Graph (, )][DBLP]


  101. Addressing Heterogeneous Bandwidth Requirements in Modified Fat-Tree Networks-on-Chips. [Citation Graph (, )][DBLP]


  102. The Fourier Spectrum Analysis of Optical Feedback Self-Mixing Signal under Weak and Moderate Feedback. [Citation Graph (, )][DBLP]


  103. Elimination of Gamma Non-linear Luminance Effects for Digital Video Projection Phase Measuring Profilometers. [Citation Graph (, )][DBLP]


  104. Integrated CMOS Analog Neural Network Ability to Linearize the Distorted Characteristic of HPA Embedded in Satellites. [Citation Graph (, )][DBLP]


  105. Compact Gray-Code Counter/Memory Circuits for Spiking Pixels. [Citation Graph (, )][DBLP]


  106. Calibration and Debugging of Multi-step Analog to Digital Converters. [Citation Graph (, )][DBLP]


  107. A Prevenient Voltage Stress Test Method for High Density Memory. [Citation Graph (, )][DBLP]


  108. A Scan-Based Delay Test Method for Reduction of Overtesting. [Citation Graph (, )][DBLP]


  109. An Integrated Validation Environment for Differential Power Analysis. [Citation Graph (, )][DBLP]


  110. Automated Testing of FlexRay Clusters for System Inconsistencies in Automotive Networks. [Citation Graph (, )][DBLP]


  111. Early Design Phase Power Performance Trade-Offs Using In-Situ Macro Models. [Citation Graph (, )][DBLP]


  112. Low Voltage Design against Power Analysis Attacks. [Citation Graph (, )][DBLP]


  113. Electrical Power Monitoring System Using Thermochron Sensor and 1-Wire Communication Protocol. [Citation Graph (, )][DBLP]


  114. Efficient VLSI Layout of Edge Product Networks. [Citation Graph (, )][DBLP]


  115. Towards a Petri Net Based Approach to Model and Synthesise Dynamic Reconfiguration for FPGAs. [Citation Graph (, )][DBLP]


  116. Arbitrary Waveform Generator Based on Direct Digital Frequency Synthesizer. [Citation Graph (, )][DBLP]


  117. Design of a Data Concentrator Card for the Readout of the Compact Muon Solenoid Electromagnetic Calorimeter. [Citation Graph (, )][DBLP]


  118. A Novel Approach to High-Level Property Checking Using Wu's Method. [Citation Graph (, )][DBLP]


  119. Test Set Stripping Limiting the Maximum Number of Specified Bits. [Citation Graph (, )][DBLP]


  120. An Automated Fault Injection Technique Based on VHDL Syntax Analysis and Stratified Sampling. [Citation Graph (, )][DBLP]


  121. CreaTe: A New Programme to Attract Engineers as Design Artists. [Citation Graph (, )][DBLP]


  122. High-Performance Pseudorandom Number Generator Using Two-Dimensional Cellular Automata. [Citation Graph (, )][DBLP]


  123. Design Automation of UHF RFID Tag Antenna Design Using a Genetic Algorithm Linked to MWS CST. [Citation Graph (, )][DBLP]

NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002