Conferences in DBLP

Defect and Fault Tolerance in VLSI Systems (dft)
2007 (conf/dft/2007)

1. 
   Reliable Network-on-Chip Using a Low Cost Unequal Error Protection Code. [Citation Graph (, )][DBLP]
   
   
2. 
   Fault Tolerant Source Routing for Network-on-Chip. [Citation Graph (, )][DBLP]
   
   
3. 
   Online NoC Switch Fault Detection and Diagnosis Using a High Level Fault Mode. [Citation Graph (, )][DBLP]
   
   
4. 
   Fault Tolerant SoC Architecture Design for JPEG2000 Using Partial Reconfigurability. [Citation Graph (, )][DBLP]
   
   
5. 
   Estimating Error Propagation Probabilities with Bounded Variances. [Citation Graph (, )][DBLP]
   
   
6. 
   A Refined Electrical Model for Particle Strikes and its Impact on SEU Prediction. [Citation Graph (, )][DBLP]
   
   
7. 
   Estimation of Electromigration-Aggravating Narrow Interconnects Using a Layout Sensitivity Model. [Citation Graph (, )][DBLP]
   
   
8. 
   SET Emulation Under a Quantized Delay Model. [Citation Graph (, )][DBLP]
   
   
9. 
   Sensitivity Evaluation of TMR-Hardened Circuits to Multiple SEUs Induced by Alpha Particles in Commercial SRAM-Based FPGAs. [Citation Graph (, )][DBLP]
   
   
10. 
    TMR and Partial Dynamic Reconfiguration to mitigate SEU faults in FPGAs. [Citation Graph (, )][DBLP]
    
    
11. 
    Optimization of Self Checking FIR filters by means of Fault Injection Analysis. [Citation Graph (, )][DBLP]
    
    
12. 
    Evaluation of Single Event Upset Mitigation Schemes for SRAM Based FPGAs Using the FLIPPER Fault Injection Platform. [Citation Graph (, )][DBLP]
    
    
13. 
    A Functional Verification Based Fault Injection Environment. [Citation Graph (, )][DBLP]
    
    
14. 
    Comparing fail-safe microcontroller architectures in light of IEC 61508. [Citation Graph (, )][DBLP]
    
    
15. 
    A Framework for Reliability Assessment and Enhancement in Multi-Processor Systems-On-Chip. [Citation Graph (, )][DBLP]
    
    
16. 
    A Defect-Tolerant Molecular-Based Memory Architecture. [Citation Graph (, )][DBLP]
    
    
17. 
    Checker Design for On-line Testing of Xilinx FPGA Communication Protocols. [Citation Graph (, )][DBLP]
    
    
18. 
    Defect-Tolerant Gate Macro Mapping & Placement in Clock-Free Nanowire Crossbar Architecture. [Citation Graph (, )][DBLP]
    
    
19. 
    Delay Fault Detection Problems in Circuits Featuring a Low Combinational Depth. [Citation Graph (, )][DBLP]
    
    
20. 
    Empirical Analysis of the Dependence of Test Power, Delay, Energy and Fault Coverage on the Architecture of LFSR-Based TPGs. [Citation Graph (, )][DBLP]
    
    
21. 
    Fault Tolerant Arithmetic Operations with Multiple Error Detection and Correction. [Citation Graph (, )][DBLP]
    
    
22. 
    Production Yield and Self-Configuration in the Future Massively Defective Nanochips. [Citation Graph (, )][DBLP]
    
    
23. 
    Test Generation for Single and Multiple Stuck-at Faults of a Combinational Circuit Designed by Covering Shared ROBDD with CLBs. [Citation Graph (, )][DBLP]
    
    
24. 
    Testing of Asynchronous NULL Conventional Logic (NCL) Circuits in Synchronous-Based Design. [Citation Graph (, )][DBLP]
    
    
25. 
    Timing-Aware Diagnosis for Small Delay Defects. [Citation Graph (, )][DBLP]
    
    
26. 
    A-Diagnosis: A Complement to Z-Diagnosis. [Citation Graph (, )][DBLP]
    
    
27. 
    Test Generation and Diagnostic Test Generation for Open Faults with Considering Adjacent Lines. [Citation Graph (, )][DBLP]
    
    
28. 
    Analysis of Specified Bit Handling Capability of Combinational Expander Networks. [Citation Graph (, )][DBLP]
    
    
29. 
    Reduction of Fault Latency in Sequential Circuits by using Decomposition. [Citation Graph (, )][DBLP]
    
    
30. 
    Soft Error Hardening for Asynchronous Circuits. [Citation Graph (, )][DBLP]
    
    
31. 
    Soft Error Hardened Latch Scheme for Enhanced Scan Based Delay Fault Testing. [Citation Graph (, )][DBLP]
    
    
32. 
    An Effective Approach for the Diagnosis of Transition-Delay Faults in SoCs, based on SBST and Scan Chains. [Citation Graph (, )][DBLP]
    
    
33. 
    Improving the Tolerance of Pipeline Based Circuits to Power Supply or Temperature Variations. [Citation Graph (, )][DBLP]
    
    
34. 
    RAM-Based Fault Tolerant State Machines for FPGAs. [Citation Graph (, )][DBLP]
    
    
35. 
    Spare Parts in Analog Circuits: A Filter Example. [Citation Graph (, )][DBLP]
    
    
36. 
    A Sharable Built-in Self-Repair for Semiconductor Memories with 2-D Redundancy Schema. [Citation Graph (, )][DBLP]
    
    
37. 
    Matrix Codes: Multiple Bit Upsets Tolerant Method for SRAM Memories. [Citation Graph (, )][DBLP]
    
    
38. 
    Reconstruction of Erasure Correcting Codes for Dependable Distributed Storage System without Spare Disks. [Citation Graph (, )][DBLP]
    
    
39. 
    Lazy Error Detection for Microprocessor Functional Units. [Citation Graph (, )][DBLP]
    
    
40. 
    Effective Checkpoint and Rollback Using Hardware/OS Collaboration. [Citation Graph (, )][DBLP]
    
    
41. 
    On-Line Periodic Self-Testing of High-Speed Floating-Point Units in Microprocessors. [Citation Graph (, )][DBLP]
    
    
42. 
    A Scalable Framework for Defect Isolation of DNA Self-assemlbled Networks. [Citation Graph (, )][DBLP]
    
    
43. 
    Error Tolerance of DNA Self-Healing Assemblies by Puncturing. [Citation Graph (, )][DBLP]
    
    
44. 
    Fault Secure Encoder and Decoder for Memory Applications. [Citation Graph (, )][DBLP]
    
    
45. 
    Safety Evaluation of NanoFabrics. [Citation Graph (, )][DBLP]
    
    
46. 
    Nanofabric PLA architecture with Redundancy Enhancement. [Citation Graph (, )][DBLP]
    
    
47. 
    Hierarchical Fault Compatibility Identification for Test Generation with a Small Number of Specified Bits. [Citation Graph (, )][DBLP]
    
    
48. 
    High Quality Test Vectors for Bridging Faults in the Presence of IC's Parameters Variations. [Citation Graph (, )][DBLP]
    
    
49. 
    Semi-Concurrent On-Line Testing of Transition Faults Through Output Response Comparison of Identical Circuits. [Citation Graph (, )][DBLP]
    
    
50. 
    Testing Reversible One-Dimensional QCA Arrays for Multiple Faults. [Citation Graph (, )][DBLP]
    
    
51. 
    Probabilistic Analysis of a Molecular Quantum-Dot Cellular Automata Adder. [Citation Graph (, )][DBLP]
    
    
52. 
    On the Error Effects of Random Clock Shifts in Quantum-Dot Cellular Automata Circuits. [Citation Graph (, )][DBLP]
    
    
53. 
    Evaluation of Register-Level Protection Techniques for the Advanced Encryption Standard by Multi-Level Fault Injections. [Citation Graph (, )][DBLP]
    
    
54. 
    Power Attacks Resistance of Cryptographic S-Boxes with Added Error Detection Circuits. [Citation Graph (, )][DBLP]
    
    
55. 
    A Fault-Tolerant Active Pixel Sensor to Correct In-Field Hot Pixel Defects. [Citation Graph (, )][DBLP]
    
    
56. 
    Quantitative Analysis of In-Field Defects in Image Sensor Arrays. [Citation Graph (, )][DBLP]