Conferences in DBLP

Euromicro Symposium on Digital Systems Design (dsd)
2007 (conf/dsd/2007)

1. 
   Design Without Borders. [Citation Graph (, )][DBLP]
   
   
2. 
   Semiconductor and EDA Challenges: Still Lots To Solve! [Citation Graph (, )][DBLP]
   
   
3. 
   Short Distance Wireless, Dense Networks, and Their Opportunities. [Citation Graph (, )][DBLP]
   
   
4. 
   Error-Aware Design. [Citation Graph (, )][DBLP]
   
   
5. 
   Ulta-Low-Power Wireless Sensor Node Design on 100 uW Scavenging Energy for Applications In Biomedical Monitoring. [Citation Graph (, )][DBLP]
   
   
6. 
   An Empirical Investigation of Mesh and Torus NoC Topologies Under Different Routing Algorithms and Traffic Models. [Citation Graph (, )][DBLP]
   
   
7. 
   Streaming consistency: a model for efficient MPSoC design. [Citation Graph (, )][DBLP]
   
   
8. 
   A FPGA Optimised Digital Real-Time Mutichannel Correlator Architecture. [Citation Graph (, )][DBLP]
   
   
9. 
   Design and Implementation of a 50MHZ DXT CoProcessor. [Citation Graph (, )][DBLP]
   
   
10. 
    A resource optimized Processor Core for FPGA based SoCs. [Citation Graph (, )][DBLP]
    
    
11. 
    Secure, Real-Time and Multi-Threaded General-Purpose Embedded Java Microarchitecture. [Citation Graph (, )][DBLP]
    
    
12. 
    Decoupling of Computation and Communication with a Communication Assist. [Citation Graph (, )][DBLP]
    
    
13. 
    An Implementation of an Address Generator Using Hash Memories. [Citation Graph (, )][DBLP]
    
    
14. 
    Experiences with a FPGA-based Reed/Solomon Encoding Coprocessor. [Citation Graph (, )][DBLP]
    
    
15. 
    Cotransformation Provides Area and Accuracy Improvement in an HDL Library for LNS Subtraction. [Citation Graph (, )][DBLP]
    
    
16. 
    General Digit-Serial Normal Basis Multiplier with Distributed Overlap. [Citation Graph (, )][DBLP]
    
    
17. 
    An efficient and optimized FPGA Feedback M-PSK Symbol Timing Recovery Architecture based on the Gardner Timing Error Detector. [Citation Graph (, )][DBLP]
    
    
18. 
    A Robust GF(p) Parallel Arithmetic Unit for Public Key Cryptography. [Citation Graph (, )][DBLP]
    
    
19. 
    A Hardware/Software Co-design vs. Hardware Implementation of the Modular Exponentiation Using the Sliding-Window Method with Constant-Length Partitioning. [Citation Graph (, )][DBLP]
    
    
20. 
    Fault Handling in FPGAs and Microcontrollers in Safety-Critical Embedded Applications: A Comparative Survey. [Citation Graph (, )][DBLP]
    
    
21. 
    Exploiting Parallelism in Double Path Adders' Structure for Increased Throughput of Floating Point Addition. [Citation Graph (, )][DBLP]
    
    
22. 
    Alternatives in Designing Level-Restoring Buffers for Interconnection Networks in Field-Programmable Gate Arrays. [Citation Graph (, )][DBLP]
    
    
23. 
    A Run-Time Scheduling Framework for a Reconfigurable Hardware Emulator. [Citation Graph (, )][DBLP]
    
    
24. 
    A Serial Logarithmic Number System ALU. [Citation Graph (, )][DBLP]
    
    
25. 
    Functional Test-Case Generation by a Control Transaction Graph for TLM Verification. [Citation Graph (, )][DBLP]
    
    
26. 
    An Embedded Implementation of the Microsoft Common Language Infrastructure. [Citation Graph (, )][DBLP]
    
    
27. 
    Evaluating the Model Accuracy in Automated Design Space Exploration. [Citation Graph (, )][DBLP]
    
    
28. 
    P-Ware: A precise and scalable component-based simulation tool for embedded multiprocessor industrial applications. [Citation Graph (, )][DBLP]
    
    
29. 
    Latency Minimization for Synchronous Data Flow Graphs. [Citation Graph (, )][DBLP]
    
    
30. 
    On Complexity of Internal and External Equivalence Checking. [Citation Graph (, )][DBLP]
    
    
31. 
    The Criteria of Functional Delay Test Quality Assessment. [Citation Graph (, )][DBLP]
    
    
32. 
    RAPANUI: A case study in Rapid Prototyping for Multiprocessor System-on-Chip. [Citation Graph (, )][DBLP]
    
    
33. 
    Functional Verification of RTL Designs driven by Mutation Testing metrics. [Citation Graph (, )][DBLP]
    
    
34. 
    Execution-time Prediction for Dynamic Streaming Applications with Task-level Parallelism. [Citation Graph (, )][DBLP]
    
    
35. 
    A New Framework for Design and Simulation of Complex Hardware/Software Systems. [Citation Graph (, )][DBLP]
    
    
36. 
    A DRAM Precharge Policy Based on Address Analysis. [Citation Graph (, )][DBLP]
    
    
37. 
    High-Accuracy Architecture-Level Power Estimation for Partitioned SRAM Arrays in a 65-nm CMOS BPTM Process. [Citation Graph (, )][DBLP]
    
    
38. 
    Controller Design and Verification for A Pipeline Image Processor based on An Extended Petri net. [Citation Graph (, )][DBLP]
    
    
39. 
    Power Estimation of Time Variant SoCs with TAPES. [Citation Graph (, )][DBLP]
    
    
40. 
    Component-Based Hardware/Software Co-Simulation. [Citation Graph (, )][DBLP]
    
    
41. 
    Toggle Equivalence Preserving (TEP) Logic Optimization. [Citation Graph (, )][DBLP]
    
    
42. 
    Design Method for Numerical Function Generators Based on Polynomial Approximation for FPGA Implementation. [Citation Graph (, )][DBLP]
    
    
43. 
    Graph Matching Constraints for Synthesis with Complex Components. [Citation Graph (, )][DBLP]
    
    
44. 
    OOCE: Object-Oriented Communication Engine for SoC Design. [Citation Graph (, )][DBLP]
    
    
45. 
    Timing- / Power-Optimization for Digital Logic Based on Standard Cells. [Citation Graph (, )][DBLP]
    
    
46. 
    Energy Based Design Space Exploration of Multiprocessor VLIW Architectures. [Citation Graph (, )][DBLP]
    
    
47. 
    Reducing the Overhead of Real-Time Operating System through Reconfigurable Hardware. [Citation Graph (, )][DBLP]
    
    
48. 
    Silicon Compaction/Defragmentation for Partial Runtime Reconfiguration. [Citation Graph (, )][DBLP]
    
    
49. 
    A Statistical Model for Estimating the Effect of Process Variations on Delay and Slew Metrics for VLSI Interconnects. [Citation Graph (, )][DBLP]
    
    
50. 
    A New Class of Cellular Automata. [Citation Graph (, )][DBLP]
    
    
51. 
    Algebraic Characterization of CNOT-Based Quantum Circuits with its Applications on Logic Synthesis. [Citation Graph (, )][DBLP]
    
    
52. 
    Analysis of Variable Reordering on the QMDD Representation of Quantum Circuits. [Citation Graph (, )][DBLP]
    
    
53. 
    Merge Logic for Clustered Multithreaded VLIW Processors. [Citation Graph (, )][DBLP]
    
    
54. 
    Automatic Generation of Low-Complexity FFT/IFFT Cores for Multi-Band OFDM Systems. [Citation Graph (, )][DBLP]
    
    
55. 
    Low-Complexity Architectures of a Decoder for IEEE 802.16e LDPC Codes. [Citation Graph (, )][DBLP]
    
    
56. 
    FPGA/DSP-based Configurable Multi-Channel Counter. [Citation Graph (, )][DBLP]
    
    
57. 
    Design and Implementation of a 90nm Low bit-rate Image Compression Core. [Citation Graph (, )][DBLP]
    
    
58. 
    FATTY: A Reliable FAT File System. [Citation Graph (, )][DBLP]
    
    
59. 
    Proving Completeness of Properties in Formal Verification of Counting Heads for Railways. [Citation Graph (, )][DBLP]
    
    
60. 
    Architecture Exploration of 3D Video Recorder Using Virtual Platform Models. [Citation Graph (, )][DBLP]
    
    
61. 
    FPGA-based Road Traffic Videodetector. [Citation Graph (, )][DBLP]
    
    
62. 
    Safety and Security-driven Design of Networked Embedded Systems. [Citation Graph (, )][DBLP]
    
    
63. 
    MPSoC memory optimization for digital camera applications. [Citation Graph (, )][DBLP]
    
    
64. 
    Architecture of a Small Low-Cost Satellite. [Citation Graph (, )][DBLP]
    
    
65. 
    FPGA Accelerating Algorithms of Active Shape Model in People Tracking Applications. [Citation Graph (, )][DBLP]
    
    
66. 
    A Sliced Coprocessor for Native Clifford Algebra Operations. [Citation Graph (, )][DBLP]
    
    
67. 
    A Hardware-Software Platform for Design and Verification of In-Motorcycle Electronic Systems. [Citation Graph (, )][DBLP]
    
    
68. 
    An Efficient Hardware Architecture for Quarter-Pixel Accurate H.264 Motion Estimation. [Citation Graph (, )][DBLP]
    
    
69. 
    An Efficient Intra Prediction Hardware Architecture for H.264 Video Decoding. [Citation Graph (, )][DBLP]
    
    
70. 
    Evaluating Energy Consumption in Wireless Sensor Networks Applications. [Citation Graph (, )][DBLP]
    
    
71. 
    Simulation Based Verification of Energy Storage Architectures for Higher Class Tags supported by Energy Harvesting Devices. [Citation Graph (, )][DBLP]
    
    
72. 
    Adaptive Distance Estimation and Localization in WSN using RSSI Measures. [Citation Graph (, )][DBLP]
    
    
73. 
    A Proposal of New Join Operators for Sensor Network Databases. [Citation Graph (, )][DBLP]
    
    
74. 
    A Wireless Sensor Node Architecture Using Remote Power Charging, for Interaction Applications. [Citation Graph (, )][DBLP]
    
    
75. 
    GigaNoC - A Hierarchical Network-on-Chip for Scalable Chip-Multiprocessors. [Citation Graph (, )][DBLP]
    
    
76. 
    On network-on-chip comparison. [Citation Graph (, )][DBLP]
    
    
77. 
    Increasing NoC Performance and Utilisation using a Dual Packet Exit Strategy. [Citation Graph (, )][DBLP]
    
    
78. 
    Effective full-duplex Mesochronous Link Architecture for Network-on-Chip Data-Link layer. [Citation Graph (, )][DBLP]
    
    
79. 
    Fully Adaptive Fault-Tolerant Routing Algorithm for Network-on-Chip Architectures. [Citation Graph (, )][DBLP]
    
    
80. 
    On-Chip Verification of NoCs Using Assertion Processors. [Citation Graph (, )][DBLP]
    
    
81. 
    Security Aspects in Networks-on-Chips: Overview and Proposals for Secure Implementations. [Citation Graph (, )][DBLP]
    
    
82. 
    NoC Topologies Exploration based on Mapping and Simulation Models. [Citation Graph (, )][DBLP]
    
    
83. 
    Application-Specific Topology Design Customization for STNoC. [Citation Graph (, )][DBLP]
    
    
84. 
    Novel Agent-Based Management for Fault-Tolerance in Network-on-Chip. [Citation Graph (, )][DBLP]
    
    
85. 
    On the impact of serialization on the cache performances in Network-on-Chip based MPSoCs. [Citation Graph (, )][DBLP]
    
    
86. 
    On the Construction of Small Fully Testable Circuits with Low Depth. [Citation Graph (, )][DBLP]
    
    
87. 
    On-Chip Cache Device Scaling Limits and Effective Fault Repair Techniques in Future Nanoscale Technology. [Citation Graph (, )][DBLP]
    
    
88. 
    Concurrent Error Detection for FSMs Designed for Implementation with Embedded Memory Blocks of FPGAs. [Citation Graph (, )][DBLP]
    
    
89. 
    Fault Injection Techniques and their Accelerated Simulation in SystemC. [Citation Graph (, )][DBLP]
    
    
90. 
    Hybrid BIST Optimization Using Reseeding and Test Set Compaction. [Citation Graph (, )][DBLP]
    
    
91. 
    Fault Diagnosis in Integrated Circuits with BIST. [Citation Graph (, )][DBLP]
    
    
92. 
    Testability Analysis Based on the Identification of Testable Blocks with Predefined Properties. [Citation Graph (, )][DBLP]
    
    
93. 
    An On-Line BIST Technique for Stuck-Open Fault Detection in CMOS Circuits. [Citation Graph (, )][DBLP]
    
    
94. 
    Test Controller Synthesis Constrained by Circuit Testability Analysis. [Citation Graph (, )][DBLP]
    
    
95. 
    Saboteur-Based Fault Injection for Quantum Circuits Fault Tolerance Assessment. [Citation Graph (, )][DBLP]
    
    
96. 
    Scaling Analytical Models for Soft Error Rate Estimation Under a Multiple-Fault Environment. [Citation Graph (, )][DBLP]
    
    
97. 
    A Low Power Information Redundant Concurrent Error Detecting Asynchronous Processor. [Citation Graph (, )][DBLP]
    
    
98. 
    Pseudo-Random Pattern Generator Design for Column-Matching BIST. [Citation Graph (, )][DBLP]
    
    
99. 
    An Efficient BIST Scheme for Non-Restoring Array Dividers. [Citation Graph (, )][DBLP]
    
    
100. 
     Hierarchical Identification of Untestable Faults in Sequential Circuits. [Citation Graph (, )][DBLP]
     
     
101. 
     The importance of At-Speed Scan Testing: an industrial experience. [Citation Graph (, )][DBLP]
     
     
102. 
     Online Protocol Testing for FPGA Based Fault Tolerant Systems. [Citation Graph (, )][DBLP]
     
     
103. 
     Performance Evaluation of Instruction Set Extensions for Long Integer Modular Arithmetic on a SPARC V8 Processor. [Citation Graph (, )][DBLP]