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Conferences in DBLP

Euromicro Symposium on Digital Systems Design (dsd)
2008 (conf/dsd/2008)

  1. Large Scale On-Chip Networks : An Accurate Multi-FPGA Emulation Platform. [Citation Graph (, )][DBLP]

  2. Network Interface Sharing Techniques for Area Optimized NoC Architectures. [Citation Graph (, )][DBLP]

  3. Efficient Application Specific Routing Algorithms for NoC Systems utilizing Partially Faulty Links. [Citation Graph (, )][DBLP]

  4. CART: Communication-Aware Routing Technique for Application-Specific NoCs. [Citation Graph (, )][DBLP]

  5. LIME: A Low-latency and Low-complexity On-chip Mesochronous Link with Integrated Flow Control. [Citation Graph (, )][DBLP]

  6. Flexible Baseband Architectures for Future Wireless Systems. [Citation Graph (, )][DBLP]

  7. A Lightweight Operating Environment for Next Generation Cognitive Radios. [Citation Graph (, )][DBLP]

  8. On Design a High Speed Sigma Delta DAC Modulator for a Digital Communication Transceiver on Chip. [Citation Graph (, )][DBLP]

  9. A Reconfigurable LFSR for Tri-standard SDR Transceiver, Architecture and Complexity Analysis. [Citation Graph (, )][DBLP]

  10. Synthesis of Flexible Fault-Tolerant Schedules with Preemption for Mixed Soft and Hard Real-Time Systems. [Citation Graph (, )][DBLP]

  11. Digital Systems Architectures Based on On-line Checkers. [Citation Graph (, )][DBLP]

  12. Fault Models and Injection Strategies in SystemC Specifications. [Citation Graph (, )][DBLP]

  13. An Efficient Multiple-Parity Generator Design for On-Line Testing on FPGA. [Citation Graph (, )][DBLP]

  14. Experimental SEU Impact on Digital Design Implemented in FPGAs. [Citation Graph (, )][DBLP]

  15. Temperature and Leakage Aware Power Control for Embedded Streaming Applications. [Citation Graph (, )][DBLP]

  16. Source-Level Estimation of Energy Consumption and Execution Time of Embedded Software. [Citation Graph (, )][DBLP]

  17. Embedded Multicore Implementation of a H.264 Decoder with Power Management Considerations. [Citation Graph (, )][DBLP]

  18. A Network-on-Chip Channel Allocator for Run-Time Task Scheduling in Multi-Processor System-on-Chips. [Citation Graph (, )][DBLP]

  19. A Network on Chip Architecture for Heterogeneous Traffic Support with Non-Exclusive Dual-Mode Switching. [Citation Graph (, )][DBLP]

  20. A Look-Ahead Task Management Unit for Embedded Multi-Core Architectures. [Citation Graph (, )][DBLP]

  21. A Modular Approach to Model Heterogeneous MPSoC at Cycle Level. [Citation Graph (, )][DBLP]

  22. Performance and Timing Yield Enhancement using Highway-on-Chip Planning. [Citation Graph (, )][DBLP]

  23. An Analysis of Connectivity and Yield for 2D Mesh Based NoC with Interconnect Router Failures. [Citation Graph (, )][DBLP]

  24. Application Specific Programmable IP Core for Motion Estimation: Technology Comparison Targeting Efficient Embedded Co-Processing Units. [Citation Graph (, )][DBLP]

  25. Analyzing Scalability of Deblocking Filter of H.264 via TLP Exploitation in a New Many-Core Architecture. [Citation Graph (, )][DBLP]

  26. Design of a Two Dimensional PRSI Image Processor. [Citation Graph (, )][DBLP]

  27. A Hardware Design for Camera-Based Power Management of Computer Monitor. [Citation Graph (, )][DBLP]

  28. Co-design and Implementation of the H.264/AVC Motion Estimation Algorithm Using Co-simulation. [Citation Graph (, )][DBLP]

  29. A Low-Cost Cache Coherence Verification Method for Snooping Systems. [Citation Graph (, )][DBLP]

  30. Dependability Evaluation of Real Railway Interlocking Device. [Citation Graph (, )][DBLP]

  31. Formulating MITF for a Multicore Processor with SEU Tolerance. [Citation Graph (, )][DBLP]

  32. Mapping a Fault-Tolerant Distributed Algorithm to Systems on Chip. [Citation Graph (, )][DBLP]

  33. Concurrent Error Detection for a Network of Combinational Logic Blocks Implemented with Memory Embedded in FPGAs. [Citation Graph (, )][DBLP]

  34. Analysis of Power Management Strategies for a Large-Scale SoC Platform in 65nm Technology. [Citation Graph (, )][DBLP]

  35. Restricted Chaining and Fragmentation Techniques in Power Aware High Level Synthesis. [Citation Graph (, )][DBLP]

  36. Power Optimization of Asynchronous Circuits through Simultaneous Vdd and Vth Assignment and Template Sizing. [Citation Graph (, )][DBLP]

  37. Why to Use Dual-Vt, If Single-Vt Serves the Purpose Better under Process Parameter Variations? [Citation Graph (, )][DBLP]

  38. Reimbursing the Handshake Overhead of Asynchronous Circuits using Compiler Pre-Synthesis Optimizations. [Citation Graph (, )][DBLP]

  39. Integrating Clock Gating and Power Gating for Combined Dynamic and Leakage Power Optimization in Digital CMOS Circuits. [Citation Graph (, )][DBLP]

  40. Leveraging Data Promotion for Low Power D-NUCA Caches. [Citation Graph (, )][DBLP]

  41. Revisiting the Cache Effect on Multicore Multithreaded Network Processors. [Citation Graph (, )][DBLP]

  42. Using Empirical Science to Engineer Systems: Optimizing Cache for Power and Performance. [Citation Graph (, )][DBLP]

  43. Reducing Leakage through Filter Cache. [Citation Graph (, )][DBLP]

  44. Communication Network Reconfiguration Overhead Optimization in Programmable Processor Array Architectures. [Citation Graph (, )][DBLP]

  45. Hardware/Software FPGA-based Network Emulator for High-speed On-board Communications. [Citation Graph (, )][DBLP]

  46. Virtual Scan Chains for Online Testing of FPGA-based Embedded Systems. [Citation Graph (, )][DBLP]

  47. Pin-limited Frequency Downscaler AHB Bridge for ASIC to FPGA Communication. [Citation Graph (, )][DBLP]

  48. Implementation of Self-Timed Circuits onto FPGAs Using Commercial Tools. [Citation Graph (, )][DBLP]

  49. PUFFIN: A Novel Compact Block Cipher Targeted to Embedded Digital Systems. [Citation Graph (, )][DBLP]

  50. Utilization of all Levels of Parallelism in a Processor Array with Subword Parallelism. [Citation Graph (, )][DBLP]

  51. Digital Nuclear Magnetic Resonance Acquisition Channel. [Citation Graph (, )][DBLP]

  52. Fast FPGA-based Trigger and Data Acquisition System for the CERN Experiment NA62: Architecture and Algorithms. [Citation Graph (, )][DBLP]

  53. A Novel Digital Ultrasound System for Experimental Research Activities. [Citation Graph (, )][DBLP]

  54. A Parallel and Modular Architecture for 802.16e LDPC Codes. [Citation Graph (, )][DBLP]

  55. WirelessUSB - Performance Analysis of an Embedded System in a Peer-to-Peer Application. [Citation Graph (, )][DBLP]

  56. Design of a Distributed Embedded System for Domotic Applications. [Citation Graph (, )][DBLP]

  57. An Embedded Acquisition System for Remote Monitoring of Tire Status in F1 Race Cars through Thermal Images. [Citation Graph (, )][DBLP]

  58. Design of a High Performance Traffic Generator on Network Processor. [Citation Graph (, )][DBLP]

  59. Implementation of Microprogrammed Hard Disk Drive Servo Sequencer. [Citation Graph (, )][DBLP]

  60. Quantum-Dot Cellular Automata Serial Comparator. [Citation Graph (, )][DBLP]

  61. Design Flow of Dynamically-Allocated Data Types in Embedded Applications Based on Elitist Evolutionary Computation Optimization. [Citation Graph (, )][DBLP]

  62. Exploiting Internal Operation Patterns during the High-Level Synthesis of Time-Constrained Circuits. [Citation Graph (, )][DBLP]

  63. Multi-Objective Statistical Yield Enhancement using Evolutionary Algorithm. [Citation Graph (, )][DBLP]

  64. Technology Library Modelling for Information-driven Circuit Synthesis. [Citation Graph (, )][DBLP]

  65. Evaluation and Improvement of Quantum Synthesis Algorithms based on a Thorough Set of Metrics. [Citation Graph (, )][DBLP]

  66. A Scheduling Postprocessor to Exploit Morphable RTL Components During High-Level Synthesis. [Citation Graph (, )][DBLP]

  67. A Novel Technique for Low Latency Data Gathering in Wireless Sensor Networks. [Citation Graph (, )][DBLP]

  68. A Solar-powered Video Sensor Node for Energy Efficient Multimodal Surveillance. [Citation Graph (, )][DBLP]

  69. Exploiting WSN for Audio Surveillance Applications: The VoWSN Approach. [Citation Graph (, )][DBLP]

  70. Code Generation from Statecharts: Simulation of Wireless Sensor Networks. [Citation Graph (, )][DBLP]

  71. Improving SER Immunity of Combinational Logic Using Combinations of Spatial and Temporal Checking. [Citation Graph (, )][DBLP]

  72. Identifying a Subset of System Verilog Assertions for Efficient Bounded Model Checking. [Citation Graph (, )][DBLP]

  73. How to Live with Uncertainties: Exploiting the Performance Benefits of Self-Timed Logic In Synchronous Design. [Citation Graph (, )][DBLP]

  74. An Efficient Non-Tree Clock Routing Algorithm for Reducing Delay Uncertainty. [Citation Graph (, )][DBLP]

  75. SDIVA: Structural Delay Insensitivity Verification Analysis Method for Bit-Level Pipelined Systolic Arrays with Early Output Evaluation. [Citation Graph (, )][DBLP]

  76. VLSI Implementation of a Cryptography-Oriented Reconfigurable Array. [Citation Graph (, )][DBLP]

  77. A New Array Fabric for Coarse-Grained Reconfigurable Architecture. [Citation Graph (, )][DBLP]

  78. Power/Area Analysis of a FPGA-Based Open-Source Processor using Partial Dynamic Reconfiguration. [Citation Graph (, )][DBLP]

  79. System-on-an-FPGA Design for Real-time Particle Track Recognition and Reconstruction in Physics Experiments. [Citation Graph (, )][DBLP]

  80. IRIS: A Firmware Design Methodology for SIMD Architectures. [Citation Graph (, )][DBLP]

  81. Measurement, Analysis and Modeling of RTOS System Calls Timing. [Citation Graph (, )][DBLP]

  82. Development of Functional Delay Tests. [Citation Graph (, )][DBLP]

  83. Application Analysis for Parallel Processing. [Citation Graph (, )][DBLP]

  84. Discrete Particle Swarm Optimization for Multi-objective Design Space Exploration. [Citation Graph (, )][DBLP]

  85. Cellflow: A Parallel Application Development Environment with Run-Time Support for the Cell BE Processor. [Citation Graph (, )][DBLP]

  86. Exploring ISS Abstractions for Embedded Software Design. [Citation Graph (, )][DBLP]

  87. High Performance Computing for Embedded System Design: A Case Study. [Citation Graph (, )][DBLP]

  88. Automatic Identification of Parallelism in Handel-C. [Citation Graph (, )][DBLP]

  89. A Variable Length Vector Pipeline Architecture Design Methodology. [Citation Graph (, )][DBLP]

  90. Ultra-Low Power Passive UHF RFID for Wireless Sensor Networks. [Citation Graph (, )][DBLP]

  91. Models and Tradeoffs in WSN System-Level Design. [Citation Graph (, )][DBLP]

  92. Pearson - based Analysis of Positioning Error Distribution in Wireless Sensor Networks. [Citation Graph (, )][DBLP]

  93. On the Need for Passive Monitoring in Sensor Networks. [Citation Graph (, )][DBLP]

  94. Efficient Test Pattern Compression Method Using Hard Fault Preferring. [Citation Graph (, )][DBLP]

  95. Digital Implementation of a BIST Method based on Binary Observations. [Citation Graph (, )][DBLP]

  96. Generating RTL Synthesizable Code from Behavioral Testbenches for Hardware-Accelerated Verification. [Citation Graph (, )][DBLP]

  97. Power Conscious RTL Test Scheduling. [Citation Graph (, )][DBLP]

  98. Hierarchical Analysis of Short Defects between Metal Lines in CMOS IC. [Citation Graph (, )][DBLP]

  99. Functional Verification of a USB Host Controller. [Citation Graph (, )][DBLP]

  100. An FPGA Implementation of a Quadruple-Based Multiplier for 4D Clifford Algebra. [Citation Graph (, )][DBLP]

  101. On the Use of Diminished-1 Adders for Weighted Modulo 2n + 1 Arithmetic Components. [Citation Graph (, )][DBLP]

  102. A New Rounding Algorithm for Variable Latency Division and Square Root Implementations. [Citation Graph (, )][DBLP]

  103. An RNS based Specific Processor for Computing the Minimum Sum-of-Absolute-Differences. [Citation Graph (, )][DBLP]

  104. Logic Transformations by Multiple Wire Network Addition. [Citation Graph (, )][DBLP]

  105. On Projecting Sums of Products. [Citation Graph (, )][DBLP]

  106. On Lookup Table Cascade-Based Realizations of Arbiters. [Citation Graph (, )][DBLP]

  107. A Fast Transformation-Based Synthesis Algorithm for Reversible Circuits. [Citation Graph (, )][DBLP]

  108. A Wireless Sensor Platform for Assistive Technology Applications. [Citation Graph (, )][DBLP]

  109. Reliable Data Transmission over Simple Wireless Channels: A Case Study. [Citation Graph (, )][DBLP]

  110. A Long-term Wearable Vital Signs Monitoring System using BSN. [Citation Graph (, )][DBLP]

  111. Design of an Ultra Low-Power RFID Baseband Processor Featuring an AES Cryptography Engine. [Citation Graph (, )][DBLP]

  112. Transaction Level Modeling and Performance Analysis in SystemC of IEEE 802.15.4 Wireless Standard. [Citation Graph (, )][DBLP]

  113. Architecture of a Power-Gated Wireless Sensor Node. [Citation Graph (, )][DBLP]

  114. A Hardware Implementation of CURUPIRA Block Cipher for Wireless Sensors. [Citation Graph (, )][DBLP]

  115. Architectural Synthesis with Control Data Flow Extraction toward an Asynchronous CAD Tool. [Citation Graph (, )][DBLP]

  116. TASTE: Testability Analysis Engine and Opened Libraries for Digital Data Path. [Citation Graph (, )][DBLP]

  117. Embedded Diagnostic Logic Test Exploiting Regularity. [Citation Graph (, )][DBLP]

  118. On the Complexity of Error Detection Functions for Redundant Residue Number Systems. [Citation Graph (, )][DBLP]

  119. Programmable Numerical Function Generators for Two-Variable Functions. [Citation Graph (, )][DBLP]

  120. SIMD Enhancements for a Hough Transform Implementation. [Citation Graph (, )][DBLP]

  121. Hardware-oriented Adaptation of a Particle Swarm Optimization Algorithm for Object Detection. [Citation Graph (, )][DBLP]

  122. Acceleration of Smith-Waterman using Recursive Variable Expansion. [Citation Graph (, )][DBLP]

  123. Maximizing Resource Utilization by Slicing of Superscalar Architecture. [Citation Graph (, )][DBLP]

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The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
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for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002