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Conferences in DBLP

Euromicro Symposium on Digital Systems Design (dsd)
2009 (conf/dsd/2009)

  1. A Dynamic Hybrid Cache Coherency Protocol for Shared-Memory MPSoC. [Citation Graph (, )][DBLP]

  2. An Efficient Hardware Architecture for Packet Re-sequencing in Network Processors MPSoCs. [Citation Graph (, )][DBLP]

  3. An Effective Replacement Strategy of Cache Memory for an SMT Processor. [Citation Graph (, )][DBLP]

  4. An Evaluation of Behaviors of S-NUCA CMPs Running Scientific Workload. [Citation Graph (, )][DBLP]

  5. A Priority-Based Budget Scheduler with Conservative Dataflow Model. [Citation Graph (, )][DBLP]

  6. Improving the Performance of the Divide-Add Fused Operation Using Variable Latency Quotient Generation. [Citation Graph (, )][DBLP]

  7. Distributed Collaborative Design of a Mixed-Signal IP Component. [Citation Graph (, )][DBLP]

  8. A Hazard-Free Delay-Insensitive 4-phase On-Chip Link Using MVCM Signaling. [Citation Graph (, )][DBLP]

  9. Improving Latency of Quantum Circuits by Gate Exchanging. [Citation Graph (, )][DBLP]

  10. Run-Time Reconfigurable Array Using Magnetic RAM. [Citation Graph (, )][DBLP]

  11. Robustness Check for Multiple Faults Using Formal Techniques. [Citation Graph (, )][DBLP]

  12. Instruction Precomputation for Fault Detection. [Citation Graph (, )][DBLP]

  13. Soft Error Tolerant Asynchronous Circuits Based on Dual Redundant Four State Logic. [Citation Graph (, )][DBLP]

  14. High Availability Fault Tolerant Architectures Implemented into FPGAs. [Citation Graph (, )][DBLP]

  15. Data Encoding for Low-Power in Wormhole-Switched Networks-on-Chip. [Citation Graph (, )][DBLP]

  16. Exploration of Slot Allocation for On-Chip TDM Virtual Circuits. [Citation Graph (, )][DBLP]

  17. Mapping Algorithms for NoC-Based Heterogeneous MPSoC Platforms. [Citation Graph (, )][DBLP]

  18. Architectural Exploration of Per-Core DVFS for Energy-Constrained On-Chip Networks. [Citation Graph (, )][DBLP]

  19. Power Management Aware Low Leakage Behavioural Synthesis. [Citation Graph (, )][DBLP]

  20. Variation-tolerant Design Using Residue Number System. [Citation Graph (, )][DBLP]

  21. Optimized Reconfigurable RTL Components for Performance Improvements During High-Level Synthesis. [Citation Graph (, )][DBLP]

  22. Combined SD-RNS Constant Multiplication. [Citation Graph (, )][DBLP]

  23. Temperature- and Cost-Aware Design of 3D Multiprocessor Architectures. [Citation Graph (, )][DBLP]

  24. Calibration Method for a CMOS 0.06mm2 150MS/s 8-bit ADC. [Citation Graph (, )][DBLP]

  25. Bootstrapped Adiabatic Complementary Pass-Transistor Logic Driver Circuit for Large Capacitive Load and Low-energy Applications. [Citation Graph (, )][DBLP]

  26. An Adaptive Unicast/Multicast Routing Algorithm for MPSoCs. [Citation Graph (, )][DBLP]

  27. Model-Driven Design of Embedded Multimedia Applications on SoCs. [Citation Graph (, )][DBLP]

  28. GridRT: A Massively Parallel Architecture for Ray-Tracing Using Uniform Grids. [Citation Graph (, )][DBLP]

  29. Using Integer Linear Programming in Test-bench Generation for Evaluating Communication Processors. [Citation Graph (, )][DBLP]

  30. Reliability Estimation Process. [Citation Graph (, )][DBLP]

  31. Time-Varying Network Fault Model for the Design of Dependable Networked Embedded Systems. [Citation Graph (, )][DBLP]

  32. Block-Level Fault Model-Free Debug and Diagnosis in Digital Systems. [Citation Graph (, )][DBLP]

  33. High Performance Image Processing on a Massively Parallel Processor Array. [Citation Graph (, )][DBLP]

  34. Thermal-Aware Test Scheduling for Core-Based SoC in an Abort-on-First-Fail Test Environment. [Citation Graph (, )][DBLP]

  35. Low Power Encoding in NoCs Based on Coupling Transition Avoidance. [Citation Graph (, )][DBLP]

  36. Hierarchical NoCs for Optimized Access to Shared Memory and IO Resources. [Citation Graph (, )][DBLP]

  37. Storage Architecture for an On-chip Multi-core Processor. [Citation Graph (, )][DBLP]

  38. Double-precision Gauss-Jordan Algorithm with Partial Pivoting on FPGAs. [Citation Graph (, )][DBLP]

  39. A Comparative Study of Parallel Prefix Adders in FPGA Implementation of EAC. [Citation Graph (, )][DBLP]

  40. Streaming Reduction Circuit. [Citation Graph (, )][DBLP]

  41. Variable Latency Rounding for Golschmidt Algorithm with Parallel Remainder Estimation. [Citation Graph (, )][DBLP]

  42. Pulse Generation for On-chip Data Transmission. [Citation Graph (, )][DBLP]

  43. High Performance Bootstrapped CMOS Dual Supply Level Shifter for 0.5V Input and 1V Output. [Citation Graph (, )][DBLP]

  44. Performance-Effective Compaction of Standard-Cell Libraries for Digital Design. [Citation Graph (, )][DBLP]

  45. On the Risk of Fault Coupling over the Chip Substrate. [Citation Graph (, )][DBLP]

  46. Heterogeneous Multiprocessor Synthesis under Performance and Reliability Constraints. [Citation Graph (, )][DBLP]

  47. A Hardware-Scheduler for Fault Detection in RTOS-Based Embedded Systems. [Citation Graph (, )][DBLP]

  48. Reliable Railway Station System Based on Regular Structure Implemented in FPGA. [Citation Graph (, )][DBLP]

  49. Dependable Controller Design Using Polymorphic Counters. [Citation Graph (, )][DBLP]

  50. Internet-Router Buffered Crossbars Based on Networks on Chip. [Citation Graph (, )][DBLP]

  51. Network-on-Chip Architecture Exploration Framework. [Citation Graph (, )][DBLP]

  52. Meta-model Assisted Optimization for Design Space Exploration of Multi-Processor Systems-on-Chip. [Citation Graph (, )][DBLP]

  53. Approximate-Timed Transactional Level Modeling for MPSoC Exploration: A Network-on-Chip Case Study. [Citation Graph (, )][DBLP]

  54. A Standardized Knobs and Monitors RTL2RTL Insertion Methodology for Fine Grain SoC Tuning. [Citation Graph (, )][DBLP]

  55. Conservative Dynamic Energy Management for Real-Time Dataflow Applications Mapped on Multiple Processors. [Citation Graph (, )][DBLP]

  56. Compilation Technique for Loop Overhead Minimization. [Citation Graph (, )][DBLP]

  57. Pipelining-Based High Throughput Low Energy Mapping on Network-on-Chip. [Citation Graph (, )][DBLP]

  58. Open Platform for Prototyping of Advanced Software Defined Radio and Cognitive Radio Techniques. [Citation Graph (, )][DBLP]

  59. Architecture and DSP Implementation of a DVB-S2 Baseband Demodulator. [Citation Graph (, )][DBLP]

  60. An Open and Reconfigurable Platform for 4G Telecommunication: Concepts and Application. [Citation Graph (, )][DBLP]

  61. Deductive Fault Simulation for Asynchronous Sequential Circuits. [Citation Graph (, )][DBLP]

  62. ARROW - A Generic Hardware Fault Injection Tool for NoCs. [Citation Graph (, )][DBLP]

  63. A Fault Tolerant NoC Architecture for Reliability Improvement and Latency Reduction. [Citation Graph (, )][DBLP]

  64. Reliability Analysis of Qubit Data Movement for Distributed Quantum Computation. [Citation Graph (, )][DBLP]

  65. High Reliable Remote Terminal Unit for Space Applications. [Citation Graph (, )][DBLP]

  66. SIMD Architectural Enhancements to Improve the Performance of the 2D Discrete Wavelet Transform. [Citation Graph (, )][DBLP]

  67. Simultaneous Multithreading VLIW DSP Architecture with Dynamic Dispatch Mechanism. [Citation Graph (, )][DBLP]

  68. Iterative Algorithm for Compound Instruction Selection with Register Coalescing. [Citation Graph (, )][DBLP]

  69. CPLD-oriented Synthesis of Finite State Machines. [Citation Graph (, )][DBLP]

  70. Architecture-Driven Synthesis of Reconfigurable Cells. [Citation Graph (, )][DBLP]

  71. An on Chip Network inside a FPGA for Run-Time Reconfigurable Low Latency Grid Communication. [Citation Graph (, )][DBLP]

  72. Composable Resource Sharing Based on Latency-Rate Servers. [Citation Graph (, )][DBLP]

  73. A MPSoC Prototyping Platform for Flexible Radio Applications. [Citation Graph (, )][DBLP]

  74. Abstract Description of System Application and Hardware Architecture for Hardware/Software Code Generation. [Citation Graph (, )][DBLP]

  75. Reconfiguration Level Analysis of FFT / FIR Units in Wireless Telecommunication Systems. [Citation Graph (, )][DBLP]

  76. Flexible Architectures for LDPC Decoders Based on Network on Chip Paradigm. [Citation Graph (, )][DBLP]

  77. High Performance CMOS 2-input NAND Based on Low-race Split-level Charge-recycling Pass-transistor Logic. [Citation Graph (, )][DBLP]

  78. Power Aware Fulfilment of Latency Requirements by Exploiting Heterogeneity in Wireless Sensor and Actuator Networks. [Citation Graph (, )][DBLP]

  79. The Case for a Balanced Decomposition Process. [Citation Graph (, )][DBLP]

  80. Heuristic Synthesis of Multi-Terminal BDDs Based on Local Width/Cost Minimization. [Citation Graph (, )][DBLP]

  81. Design, Simulation and Performance Evaluation of a NAND Based Single-electron 2-4 Decoder. [Citation Graph (, )][DBLP]

  82. Adaptive Dynamic Voltage and Frequency Scaling Algorithm for Symmetric Multiprocessor Architecture. [Citation Graph (, )][DBLP]

  83. Survey of Test Data Compression Technique Emphasizing Code Based Schemes. [Citation Graph (, )][DBLP]

  84. A Concept for Logic Self Repair. [Citation Graph (, )][DBLP]

  85. A Synthesisable Quasi-Delay Insensitive Result Forwarding Unit for an Asynchronous Processor. [Citation Graph (, )][DBLP]

  86. An Efficient Low-Complexity Alternative to the ROB for Out-of-Order Retirement of Instructions. [Citation Graph (, )][DBLP]

  87. An Effective Methodology to Multi-objective Design of Application Domain-specific Embedded Architectures. [Citation Graph (, )][DBLP]

  88. Energy and Performance Model of a SPARC Leon3 Processor. [Citation Graph (, )][DBLP]

  89. Acceleration of MELP Algorithm Using DSP Coprocessor with Extended Registers. [Citation Graph (, )][DBLP]

  90. FPGA Accelerator for RNA Secondary Structure Prediction. [Citation Graph (, )][DBLP]

  91. An FPGA-Based Embedded System for Fingerprint Matching Using Phase-Only Correlation Algorithm. [Citation Graph (, )][DBLP]

  92. xMAML: A Modeling Language for Dynamically Reconfigurable Architectures. [Citation Graph (, )][DBLP]

  93. A High Performance Hardware Architecture for One Bit Transform Based Motion Estimation. [Citation Graph (, )][DBLP]

  94. Memory Conflict Analysis and Interleaver Design for Parallel Turbo Decoding Supporting HSPA Evolution. [Citation Graph (, )][DBLP]

  95. GPU Accelerated Solver of Time-Dependent Air Pollutant Transport Equations. [Citation Graph (, )][DBLP]

  96. A Reconfigurable Frame Interpolation Hardware Architecture for High Definition Video. [Citation Graph (, )][DBLP]

  97. Transactions Sequence Tracking by means of Dynamic Binary Instrumentation of TLM Models. [Citation Graph (, )][DBLP]

  98. Design of a Highly Dependable Beamforming Chip. [Citation Graph (, )][DBLP]

  99. One Dimensional Systolic Inversion Architecture Based on Modified GF(2^k) Extended Euclidean Algorithm. [Citation Graph (, )][DBLP]

  100. Signal Integrity and Power Integrity Methodology for Robust Analysis of On-the-Board System for High Speed Serial Links. [Citation Graph (, )][DBLP]

  101. Synthesizing Reversible Circuits for Irreversible Functions. [Citation Graph (, )][DBLP]

  102. A Fast SOP Minimizer for Logic Funcions Described by Many Product Terms. [Citation Graph (, )][DBLP]

  103. Representation of Incompletely Specified Index Generation Functions Using Minimal Number of Compound Variables. [Citation Graph (, )][DBLP]

  104. Logic Minimization and Testability of 2SPP-P-Circuits. [Citation Graph (, )][DBLP]

  105. FPGA Implementations of SHA-3 Candidates: CubeHash, Grostl, LANE, Shabal and Spectral Hash. [Citation Graph (, )][DBLP]

  106. Recursive Systematic Convolutional Code Simulation for Ofdm - 802.11p System and FPGA Implementation Using an ESL Methodology. [Citation Graph (, )][DBLP]

  107. Stereo Vision Algorithm Implementation in FPGA Using Census Transform for Effective Resource Optimization. [Citation Graph (, )][DBLP]

  108. The Parallel Sieve Method for a Virus Scanning Engine. [Citation Graph (, )][DBLP]

  109. Low-Power Low-Energy Prime-Field ECC Processor Based on Montgomery Modular Inverse Algorithm. [Citation Graph (, )][DBLP]

  110. Methodology for Fast Pattern Matching by Deterministic Finite Automaton with Perfect Hashing. [Citation Graph (, )][DBLP]

  111. An FPGA-Based Embedded System for a Sailing Robot. [Citation Graph (, )][DBLP]

  112. Ad-hoc WSN in Biological Research. [Citation Graph (, )][DBLP]

  113. Low Power Free Space Optical Communication in Wireless Sensor Networks. [Citation Graph (, )][DBLP]

  114. A Framework for Compile-time and Run-time Management of Non-functional Aspects in WSNs Nodes. [Citation Graph (, )][DBLP]

  115. Remote Monitoring of Thermal Performance of Salinity Gradient Solar Ponds. [Citation Graph (, )][DBLP]

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for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002