The SCEAS System
Navigation Menu

Conferences in DBLP

Engineering of Reconfigurable Systems and Algorithms (ERSA) (ersa)
2009 (conf/ersa/2009)

  1. Algorithm Design for Reconfigurable Computing Systems. [Citation Graph (, )][DBLP]

  2. It's Like Deja-Vu All over Again ... Again. [Citation Graph (, )][DBLP]

  3. Future Directions in Reconfigurable Computing. [Citation Graph (, )][DBLP]

  4. FPGA Prototyping Approach for the Validation of Efficient Iterative Decoders in Digital Communication Systems. [Citation Graph (, )][DBLP]

  5. Japanese Dynamically Reconfigurable Processors. [Citation Graph (, )][DBLP]

  6. How Constrains Programming Can Help You in the Generation of Optimized Application Specific Reconfigurable Processor Extensions. [Citation Graph (, )][DBLP]

  7. Bio-inspired Systems: Self-adaptability from Chips to Sensor-network Architectures. [Citation Graph (, )][DBLP]

  8. Adaptive Multicore Systems-on-Chip (MSoC) - Design and Computing in the Nano Era. [Citation Graph (, )][DBLP]

  9. A Design Environment for Bio-Inspired Cellular Architectures. [Citation Graph (, )][DBLP]

  10. Networked Self-adaptive Systems: An Opportunity for Configuring in the Large. [Citation Graph (, )][DBLP]

  11. Adaptive Processing Architectures for the Ultimate Scaling of the CMOS World. [Citation Graph (, )][DBLP]

  12. Element CXI: Exploring Element Computing in Academia. [Citation Graph (, )][DBLP]

  13. The Effect of Parameterization on a Reconfigurable Implementation of PIV. [Citation Graph (, )][DBLP]

  14. Configuration with Self-Configured Datapath: A High Speed Configuration Method for Dynamically Reconfigurable Processors. [Citation Graph (, )][DBLP]

  15. Using Run-time Reconfiguration for Energy Savings in Parallel Data Processing. [Citation Graph (, )][DBLP]

  16. Application Experiments: MPPA and FPGA. [Citation Graph (, )][DBLP]

  17. Bit Error Rate, Power and Area Analysis of Multiple FPGA Implementations of Underwater FSK. [Citation Graph (, )][DBLP]

  18. An Asynchronous Field-Programmable VLSI Using LEDR/4-Phase-Dual-Rail Protocol Converters. [Citation Graph (, )][DBLP]

  19. A Systolic String Matching Algorithm for High-Speed Recognition of a Restricted Regular Set. [Citation Graph (, )][DBLP]

  20. A Novel Multicontext Coarse-Grained Join Accelerator for Column-Oriented Databases. [Citation Graph (, )][DBLP]

  21. Towards Effective Modeling and Programming Multi-core Tiled Reconfigurable Architectures. [Citation Graph (, )][DBLP]

  22. SiLLis: A Simplified Language for Monitoring and Debugging of Reconfigurable Systems. [Citation Graph (, )][DBLP]

  23. Supporting Operating Systems for Reconfigurable Computing: A Distributed Service Oriented Approach. [Citation Graph (, )][DBLP]

  24. Harnessing Human Computation Cycles for the FPGA Placement Problem. [Citation Graph (, )][DBLP]

  25. Programming Model and Low-level Language for a Coarse-Grained Reconfigurable Multimedia Processor. [Citation Graph (, )][DBLP]

  26. The Speedy DDR2 Controller For FPGAs. [Citation Graph (, )][DBLP]

  27. An Implementation of Security Extensions for Data Integrity and Confidentiality in Soft-Core Processors. [Citation Graph (, )][DBLP]

  28. A Scalable H.264/AVC Variable Block Size Motion Estimation Engine Using Partial Reconfiguration. [Citation Graph (, )][DBLP]

  29. High Efficiency Reconfigurable Cache for Image Processing. [Citation Graph (, )][DBLP]

  30. An Efficient Comparative Evaluation to Buffering Methods for Window-based Image Processing Using Semi-programmable Hardware. [Citation Graph (, )][DBLP]

  31. Implementation of the Gauss-Newton Algorithm for Non-linear Least-mean-squares Fitting in FPGA Devices. [Citation Graph (, )][DBLP]

  32. High-efficiency FPGA Fully-Based Implementation of the Conjugate Gradient Method. [Citation Graph (, )][DBLP]

  33. Hardware-Optimized Ziggurat Algorithm for High-Speed Gaussian Random Number Generators. [Citation Graph (, )][DBLP]

  34. FPGA Implementation of a High-Speed Stereo Matching Processor Based on Recursive Computation. [Citation Graph (, )][DBLP]

  35. A Multi-Application Mapping Framework for Network-on-Chip Based MPSoC: An FPGA Implementation Case Study. [Citation Graph (, )][DBLP]

  36. A Fine-Grain SIMD Architecture Based on Flexible Ferroelectric-Capacitor Logic. [Citation Graph (, )][DBLP]

  37. Fault Avoidance in Medium-Grain Reconfigurable Hardware Architectures. [Citation Graph (, )][DBLP]

  38. Transformable Vertexes Information based Algorithm for Online Task Placement in Reconfigurable System. [Citation Graph (, )][DBLP]

  39. A Real Chip Evaluation of MuCCRA-3: A Low Power Dycamically Reconfigurable Processor Array. [Citation Graph (, )][DBLP]

  40. FPGA-architecture for Knowledge-Based Target Detection in Radar Signal Processing. [Citation Graph (, )][DBLP]

  41. Acceleration of Optical-Flow Extraction Using Dynamically Reconfigurable ALU Arrays. [Citation Graph (, )][DBLP]

  42. Nanocomputing Block based Multi-Context FPGA. [Citation Graph (, )][DBLP]

  43. Optimizing the FPGA Memory Design for a Sobel Edge Detector. [Citation Graph (, )][DBLP]

  44. High-Level Exploration for Dynamic Reconfiguration Management. [Citation Graph (, )][DBLP]

  45. An FPGA Implementation of an Elliptic Curve Cryptosystem Coprocessor over Prime Fields. [Citation Graph (, )][DBLP]

  46. A Multi-Context Programmable Optically Reconfigurable Gate Array. [Citation Graph (, )][DBLP]

  47. Optically Reconfigurable Gate Array with a One-Time Writable Holographic Memory. [Citation Graph (, )][DBLP]

  48. Lost in Space! Quantifying the Elements of FPGA Speedup. [Citation Graph (, )][DBLP]

  49. Improved gradient-based motion estimation on reconfigurable platforms. [Citation Graph (, )][DBLP]

  50. Woolcano: An Architecture And Tool Flow For Dynamic Instruction Set Extension On Xilinx Virtex-4 FX. [Citation Graph (, )][DBLP]

  51. Data path Configuration Time Reduction for Run-time Reconfigurable Systems. [Citation Graph (, )][DBLP]

  52. Area Evaluation for Parallel Execution in Reconfigurable Processor Architectures. [Citation Graph (, )][DBLP]

  53. Alignment compensation method for an optically reconfigurable gate array. [Citation Graph (, )][DBLP]

System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
System created by [] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002