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Conferences in DBLP

Engineering of Reconfigurable Systems and Algorithms (ERSA) (ersa)
2007 (conf/ersa/2007)


  1. Challenges in Consumer Electronics for the 21st Century. [Citation Graph (, )][DBLP]


  2. Scientific Computing using Reconfigurable Hardware. [Citation Graph (, )][DBLP]


  3. A Unified Retargetable Design Methodology for Dedicated and Re-Programmable Multiprocessor Arrays: Case Study and Quantitative Evaluation. [Citation Graph (, )][DBLP]


  4. An Integrated Platform for Heterogeneous Reconfigurable Computing. [Citation Graph (, )][DBLP]


  5. Energy-Efficient Dynamic Task Scheduling Algorithm for Reconfigurable System-on-Chip Architectures. [Citation Graph (, )][DBLP]


  6. Memory Hierarchy for MCSoPC Multithreaded Systems. [Citation Graph (, )][DBLP]


  7. Design Space Exploration of Multiprocessor Systems with MultiContext Reconfigurable Co-Processors. [Citation Graph (, )][DBLP]


  8. Energy-Aware System Synthesis for Reconfigurable Chip Multiprocessors. [Citation Graph (, )][DBLP]


  9. HW implementation of an execution manager for reconfigurable systems. [Citation Graph (, )][DBLP]


  10. Task Partitioning for the Scheduling on Reconfigurable Systems driven by Specification Self-Similarity. [Citation Graph (, )][DBLP]


  11. Configuration and Data Scheduling for Executing Dynamic Applications onto Multi-Context Reconfigurable Architectures. [Citation Graph (, )][DBLP]


  12. A Compiler to Generate Hardware from Java Byte Codes for High Performance, Low Energy Embedded Systems. [Citation Graph (, )][DBLP]


  13. Selecting Heterogeneous Computation Blocks for Reconfigurable JPEG Codec Computing. [Citation Graph (, )][DBLP]


  14. High-Precision BLAS on FPGA-enhanced Computers. [Citation Graph (, )][DBLP]


  15. High-efficiency protection solution for off-chip memory in embedded systems. [Citation Graph (, )][DBLP]


  16. Simulation Framework for Performance Prediction in the Engineering of Reconfigurable Systems and Applications. [Citation Graph (, )][DBLP]


  17. FPGA Implementation of an Analytical Design Method for A Cycle-Optimal 2D-DCT/IDCT. [Citation Graph (, )][DBLP]


  18. Prototyping of a Two-Phase Micropipeline on FPGAs. [Citation Graph (, )][DBLP]


  19. A New Routing Approach to Minimizing FPGA Reconfiguration Data. [Citation Graph (, )][DBLP]


  20. Latency Optimization for a Reconfigurable, Self-Timed, and Bit-Serial Architecture. [Citation Graph (, )][DBLP]


  21. An FPGA Implementation of Reciprocal Sums for SPME. [Citation Graph (, )][DBLP]


  22. Optimization of Shared High-Performance Reconfigurable Computing Resources. [Citation Graph (, )][DBLP]


  23. Computation Patterns Identification for Instruction Set Extensions Implemented as Reconfigurable Hardware. [Citation Graph (, )][DBLP]


  24. Critical Path Delay Reduction in FPGAs with Unbalanced Lookup Times. [Citation Graph (, )][DBLP]


  25. Reducing the reconfiguration overhead: a survey of techniques. [Citation Graph (, )][DBLP]


  26. Implementing the G.723.1 Speech Codec Using a Coarse-Grained Reconfigurable Coprocessor. [Citation Graph (, )][DBLP]


  27. Exploring Partial Reconfiguration for Mitigating SEU faults in SRAM-Based FPGAs. [Citation Graph (, )][DBLP]


  28. Performance Analysis of Multi-process Execution Model on Dynamically Reconfigurable Processor. [Citation Graph (, )][DBLP]


  29. Agent-Based Reconfigurability for Fault-Tolerance in Network-on-Chip. [Citation Graph (, )][DBLP]


  30. Design and Evaluation of a Software Infrastructure for the Runtime Management of Reconfigurable Resources. [Citation Graph (, )][DBLP]


  31. Evolvable Hardware: A Functional Level Evolution Framework Based on ImpulseC. [Citation Graph (, )][DBLP]


  32. Autonomous Computing Systems: A Proposed Roadmap. [Citation Graph (, )][DBLP]


  33. A TCP/IP Fragmentation Monitoring Core For Intrusion Prevention. [Citation Graph (, )][DBLP]


  34. Pure ASIC-Based Retargetable Computing: Architectures, Advantages, and Challenges. [Citation Graph (, )][DBLP]


  35. Design of Homogeneous Communication Infrastructures for Partially Reconfigurable FPGAs. [Citation Graph (, )][DBLP]


  36. A Sandbox for Exploring the OpenFire Processor. [Citation Graph (, )][DBLP]


  37. Power Efficient Domain-Specific Reconfigurable Architectures for System-on-Chip Applications. [Citation Graph (, )][DBLP]


  38. 272 Gate Count Optically Differential Reconfigurable Gate Array VLSI. [Citation Graph (, )][DBLP]


  39. FPGA Implementation of a Reconfigurable License Plate Detection Method. [Citation Graph (, )][DBLP]


  40. Performance Evaluation of Two Allocation Schemes for Combinatorial Group Testing Fault Isolation. [Citation Graph (, )][DBLP]


  41. Efficient FPGA-based Implementation of Time Synchronization for MIMO-OFDM. [Citation Graph (, )][DBLP]


  42. High-Level Specification of Runtime Reconfigurable Designs. [Citation Graph (, )][DBLP]


  43. A Scalable and Reconfigurable Shared-Memory Graphics Cluster Architecture. [Citation Graph (, )][DBLP]


  44. Optimization of Reconfiguration-speed Control Bits for an Optically Reconfigurable Gate Array. [Citation Graph (, )][DBLP]


  45. Feasibility of Hardware Acceleration of a Neocortex Model. [Citation Graph (, )][DBLP]


  46. Autonomous Computing Systems: A Proof-of-Concept. [Citation Graph (, )][DBLP]

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