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Conferences in DBLP

Engineering of Reconfigurable Systems and Algorithms (ERSA) (ersa)
2008 (conf/ersa/2008)

  1. Multicore Devices: A New Generation of Reconfigurable Architectures. [Citation Graph (, )][DBLP]

  2. Reconfigurable Mesh Techniques and Applications. [Citation Graph (, )][DBLP]

  3. On FPGA Design with Self-checking and Fault Tolerance Capability. [Citation Graph (, )][DBLP]

  4. The GOmputer: Accelerating GO with FPGAs. [Citation Graph (, )][DBLP]

  5. Modeling Abstractions for Next Generation Reconfigurable Computing. [Citation Graph (, )][DBLP]

  6. Design Productivity for Configurable Computing. [Citation Graph (, )][DBLP]

  7. FPGAs or Distributed Systems? [Citation Graph (, )][DBLP]

  8. A New Tact in Reconfigurable Computing Research. [Citation Graph (, )][DBLP]

  9. Industrial Workshop - Architectural Synthesis for Reconfigurable Computing. [Citation Graph (, )][DBLP]

  10. Communication and Synchronization in Multithreaded Reconfigurable Computing Systems. [Citation Graph (, )][DBLP]

  11. A New High Performance Multi Gigabit String Matching Engine. [Citation Graph (, )][DBLP]

  12. Towards Understanding and Managing the Dynamic Behavior of Run-Time Reconfigurable Architectures. [Citation Graph (, )][DBLP]

  13. System on a Programmable Chip Adaptation Through Active Partial Reconfiguration. [Citation Graph (, )][DBLP]

  14. A New Efficient Architecture for Univariate Polynomial Interpolation Over GF(2m). [Citation Graph (, )][DBLP]

  15. A Quantitative Study of the Routing Architecture Exploring Routing Locality Property for Better Performance and Routability. [Citation Graph (, )][DBLP]

  16. Design Framework for Partial Run-Time FPGA Reconfiguration. [Citation Graph (, )][DBLP]

  17. Elemental Computing for High Reliability. [Citation Graph (, )][DBLP]

  18. An Introduction to Radiation-Induced Failure Modes and Related Mitigation Methods For Xilinx SRAM FPGAs. [Citation Graph (, )][DBLP]

  19. Multiparadigm Computing for Space-Based Synthetic Aperture Radar. [Citation Graph (, )][DBLP]

  20. TMR with More Frequent Voting for Improved FPGA Reliability. [Citation Graph (, )][DBLP]

  21. Highly Parallel FPGA Based IEEE-754 Compliant Double-Precision Floating-Point Division. [Citation Graph (, )][DBLP]

  22. SystemC-based Custom Reconfigurable Cores for Wireless Applications. [Citation Graph (, )][DBLP]

  23. A Formal Semantics for Control and Data flow in the Gannet Service-based System-on-Chip Architecture. [Citation Graph (, )][DBLP]

  24. Optimizing Pipelining in HDL Generated Automatically from C Source Codes. [Citation Graph (, )][DBLP]

  25. A Framework to Improve IP Portability on Reconfigurable Computers. [Citation Graph (, )][DBLP]

  26. Implementation of a Multi-Context FPGA Based on Flexible-Context-Partitioning. [Citation Graph (, )][DBLP]

  27. A Method for Capturing State Data on Dynamically Reconfigurable Processors. [Citation Graph (, )][DBLP]

  28. Evaluation of MuCCRA-D: A Dynamically Reconfigurable Processor with Directly Interconnected PEs. [Citation Graph (, )][DBLP]

  29. MISC: Mono Instruction-Set Computer based on Dynamic Reconfiguration - a 6502 Perspective. [Citation Graph (, )][DBLP]

  30. Fast Real-Time LIDAR Processing on FPGAs. [Citation Graph (, )][DBLP]

  31. Gradient Run-length Data Compression for Real-time Airborne Image Processing. [Citation Graph (, )][DBLP]

  32. A Hardware Accelerator for k-th Nearest Neighbor Thinning. [Citation Graph (, )][DBLP]

  33. A Parallel Array to Accelerate GFA Modeling in Video Coding. [Citation Graph (, )][DBLP]

  34. Qnet: A Modular Architecture for Reconfigurable Computing. [Citation Graph (, )][DBLP]

  35. Scalable FPGA Architecture for DCT Computation Using Dynamic Partial Reconfiguration. [Citation Graph (, )][DBLP]

  36. SCARS: Scalable Self-Configurable Architecture for Reusable Space Systems. [Citation Graph (, )][DBLP]

  37. Selection and Use of Programmable Logic in Flight Applications. [Citation Graph (, )][DBLP]

  38. Hardware/Software Co-designed Extended Kalman Filter on an FPGA. [Citation Graph (, )][DBLP]

  39. Multi-Criteria Optimization and Performance Measurement of Domain-Specific Reconfigurable Architectures Targeting Image and Video Processing Applications. [Citation Graph (, )][DBLP]

  40. A 770ns Holographic Reconfiguration of a Four-Context DORGA. [Citation Graph (, )][DBLP]

  41. Dynamically Reconfigurable FFTs for Cognitive Radio on a Multiprocessor Platform. [Citation Graph (, )][DBLP]

  42. High Performance Double Precision Reduction Circuit Implementation in FPGA. [Citation Graph (, )][DBLP]

  43. A Cellular Automata ASIC for Conformal Computing. [Citation Graph (, )][DBLP]

  44. Synthesis of relocatable tasks and implementation of a task communication bus in a general purpose Hw system. [Citation Graph (, )][DBLP]

  45. Non-Volatile Multi-Context FPGAs Using Hybrid Multiple-Valued/Binary Context Switching Signals. [Citation Graph (, )][DBLP]

  46. FPGA Schemes with Optimized Routing for the Advanced Encryption Standard. [Citation Graph (, )][DBLP]

  47. Performance Evaluation of FPGA-based Hardware Accelerator: A Case Study. [Citation Graph (, )][DBLP]

  48. FPGA Resource Management Using Internal RAM as Aata Cache. [Citation Graph (, )][DBLP]

  49. Resource Management for Hw Multitasking in Three Dimensional FPGAs. [Citation Graph (, )][DBLP]

  50. The Viability of Cellular Automata Architectures for General Purpose Computing. [Citation Graph (, )][DBLP]

  51. Threats and Challenges in Reconfigurable Hardware Security. [Citation Graph (, )][DBLP]

  52. High Level Languages for Reconfigurable Computing: An Equivalent to Third Generation Software Languages? [Citation Graph (, )][DBLP]

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