Conferences in DBLP
George Alexiou , Dimitrios Stiliadis , Nick Kanopoulos Design and Implementation of a High-Performance, Modular, Sorting Engine. [Citation Graph (0, 0)][DBLP ] Conf ] Alain Greiner , L. Lucas , Franck Wajsbürt , Laurent Winckel Design of a High Complexity Superscalar Microprocessor with the Portable IDPS ASIC Library. [Citation Graph (0, 0)][DBLP ] Conf ] T. Michel , Régis Leveugle , Gabriele Saucier , R. Doucet , P. Chapier Taking Advantage of ASICs to Improve Dependability with Very Low Overheads. [Citation Graph (0, 0)][DBLP ] Conf ] Frank H. M. Franssen , Lode Nachtergaele , H. Samsom , Francky Catthoor , Hugo De Man Control flow optimization for fast system simulation and storage minimization. [Citation Graph (0, 0)][DBLP ] Conf ] Shan-Hsi Huang , Jan M. Rabaey Maximizing the Throughput of High Performance DSP Applications Using Behavioral Transformations. [Citation Graph (0, 0)][DBLP ] Conf ] Clifford Liem , Trevor C. May , Pierre G. Paulin Instruction-Set Matching and Selection for DSP and ASIP Code Generation. [Citation Graph (0, 0)][DBLP ] Conf ] Elizabeth M. Rudnick , John G. Holm , Daniel G. Saab , Janak H. Patel Application of Simple Genetic Algorithms to Sequential Circuit Test Generation. [Citation Graph (0, 0)][DBLP ] Conf ] Silvano Gai , Pier Luca Montessoro , Matteo Sonza Reorda TORSIM: An Efficient Fault Simulator for Synchronous Sequential Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Franco Fummi , Donatella Sciuto , Micaela Serra A Functional Approach to Delay Faults Test Generation for Sequential Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Huy Nam Nguyen , J. P. Tual , L. Ducousso , M. Thill , P. Vallet Logic Synthesis and Verification of the CPU and Caches of a Mainframe System. [Citation Graph (0, 0)][DBLP ] Conf ] Fermín Calvo , Pierre Plaza , Pedro Mateos ICM2 IC: a new ATM switching element for 2.48 Gb/s communications. [Citation Graph (0, 0)][DBLP ] Conf ] R. van Dongen , V. Rikkink Advanced Analog Circuit Design on a Digital Sea-of-Gates Array. [Citation Graph (0, 0)][DBLP ] Conf ] Dorine Gevaert , Jozef Vanneuville , Jiri Nedved , Jan Sevenhans Switched Current Sigma-Delta A/D Converter for a CMOS Subscriber Line Analog Front End. [Citation Graph (0, 0)][DBLP ] Conf ] Hitesh Ajuha , Premachandran R. Menon Delay Reduction by Segment Substitution. [Citation Graph (0, 0)][DBLP ] Conf ] Bernhard Rohfleisch , Franc Brglez Introduction of Permissible Bridges with Application to Logic Optimization after Technology Mapping. [Citation Graph (0, 0)][DBLP ] Conf ] Lakshmikanth Ghatraju , Mostafa H. Abd-El-Barr , Carl McCrosky High-Level Synthesis of Digital Circuits by Finding Fixpoints. [Citation Graph (0, 0)][DBLP ] Conf ] Daniel R. Brasen , Gabriele Saucier FPGA Partitioning for Critical Paths. [Citation Graph (0, 0)][DBLP ] Conf ] Sen-Pin Lin , Sandeep K. Gupta , Melvin A. Breuer A Low Cost BIST Methodology and Associated Novel Test Pattern Generator. [Citation Graph (0, 0)][DBLP ] Conf ] Albrecht P. Stroele Signature Analysis for Sequential Circuits with Reset. [Citation Graph (0, 0)][DBLP ] Conf ] Ian G. Harris , Alex Orailoglu Fine-Grained Concurrency in Test Scheduling for Partial-Intrusion BIST. [Citation Graph (0, 0)][DBLP ] Conf ] R. J. Illman , D. J. Traynor A Fragmented Register Architecture and Test Advisor for BIST. [Citation Graph (0, 0)][DBLP ] Conf ] Ben Chen , Michihiro Yamazaki , Masahiro Fujita Bug Identification of a Real Chip Design by Symbolic Model Checking. [Citation Graph (0, 0)][DBLP ] Conf ] Hyunwoo Cho , Gary D. Hachtel , Enrico Macii , Massimo Poncino , Fabio Somenzi A State Space Decomposition Algorithm for Approximate FSM Traversal. [Citation Graph (0, 0)][DBLP ] Conf ] Johannes Helbig , Peter Kelb An OBDD-Representation of Statecharts. [Citation Graph (0, 0)][DBLP ] Conf ] Andrej Zemva , Franc Brglez , Krzysztof Kozminski , Baldomir Zajc A Functionality Fault Model: Feasibility and Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Michele Favalli , Marcello Dalpasso , Piero Olivo , Bruno Riccò Modeling of Broken Connections Faults in CMOS ICs. [Citation Graph (0, 0)][DBLP ] Conf ] Brian Chess , Tracy Larrabee Generating Test Patterns for Bridge Faults in CMOS ICs. [Citation Graph (0, 0)][DBLP ] Conf ] Ralf Hahn , Rolf Krieger , Bernd Becker A Hierarchical Approach to Fault Collapsing. [Citation Graph (0, 0)][DBLP ] Conf ] Kuan-Jen Lin , Jih-Wen Kuo , Chen-Shang Lin Direct Synthesis of Hazard-Free Asynchronous Circuits from STGs Based on Lock Relation and BG-Decomposition Approach. [Citation Graph (0, 0)][DBLP ] Conf ] Yosinori Watanabe , Robert K. Brayton State Minimization of Pseudo Non-Deterministic FSM's. [Citation Graph (0, 0)][DBLP ] Conf ] Maurizio Damiani Nondeterministic finite-state machines and sequential don't cares . [Citation Graph (0, 0)][DBLP ] Conf ] Jochen Bern , Jordan Gergov , Christoph Meinel , Anna Slobodová Boolean Manipulation with Free BDD's. First Experimental Results. [Citation Graph (0, 0)][DBLP ] Conf ] Michel Langevin , Eduard Cerny An Extended OBDD Representation for Extended FSMs. [Citation Graph (0, 0)][DBLP ] Conf ] Gary D. Hachtel , Enrico Macii , Abelardo Pardo , Fabio Somenzi Symbolic Algorithms to Calculate Steady-State Probabilities of a Finite State Machine. [Citation Graph (0, 0)][DBLP ] Conf ] Oliver F. Haberl , Thomas Kropf Self Testable Boards with Standard IEEE 1149.5 Module Test and Maintenance (MTM) Bus Interface. [Citation Graph (0, 0)][DBLP ] Conf ] Chauchin Su Random Testing of Interconnects in A Boundary Scan Environment. [Citation Graph (0, 0)][DBLP ] Conf ] Matti Kärkkäinen , Kari Tiensyrjä , Matti Weissenfelt Boundary Scan Testing Combined with Power Supply Current Monitoring. [Citation Graph (0, 0)][DBLP ] Conf ] Roberto Sarmiento , Kamran Eshraghian Implementation of a CORDIC Processor for CFFT Computation in Gallium Arsenide Technology. [Citation Graph (0, 0)][DBLP ] Conf ] Pierre Coulomb , François Pogodalla PLFP256 A Pipelined Fourier Processor. [Citation Graph (0, 0)][DBLP ] Conf ] A. Vacher , M. Benkhebbab , Alain Guyot , T. Rousseau , Ali Skaf A VLSI Implementation of Parallel Fast Fourier Transform. [Citation Graph (0, 0)][DBLP ] Conf ] D. Jacquet , Gabriele Saucier Design of a Digital Neural Chip: Application to Optical Character Recognition by Neural Network. [Citation Graph (0, 0)][DBLP ] Conf ] Loganath Ramachandran , Daniel Gajski , Viraphol Chaiyakul An Algorithm for Array Variable Clustering. [Citation Graph (0, 0)][DBLP ] Conf ] Mani B. Srivastava , Miodrag Potkonjak Transforming Linear Systems for Joint Latency and Throughout Optimization. [Citation Graph (0, 0)][DBLP ] Conf ] Sandeep Bhatia , Niraj K. Jha Genesis: A Behavioral Synthesis System for Hierarchical Testability. [Citation Graph (0, 0)][DBLP ] Conf ] Tsung-Yi Wu , Tzu-Chie Tien , Allen C.-H. Wu , Youn-Long Lin A Synthesis Method for Mixed Synchronous / Asynchronous Behavior. [Citation Graph (0, 0)][DBLP ] Conf ] Anton Vuksic , Karl Fuchs A New BIST Approach for Delay Fault Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Chih-Ang Chen , Sandeep K. Gupta BIST Test Pattern Generators for Stuck-Open and Delay Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Wuudiann Ke , Premachandran R. Menon Synthesis of Delay-Verifiable Two-Level Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Sying-Jyan Wang Synthesis of Sequential Machines with Reduced Testing Cost. [Citation Graph (0, 0)][DBLP ] Conf ] Champaka Ramachandran , Fadi J. Kurdahi Incorporating the Controller Effects During Register Transfer Level Synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Nancy D. Holmes , Daniel Gajski An Algorithm for Generation of Behavioral Shape Functions. [Citation Graph (0, 0)][DBLP ] Conf ] Mehmet Emin Dalkiliç , Vijay Pitchumani Optimal Operation Scheduling Using Resource Lower Bound Estimations. [Citation Graph (0, 0)][DBLP ] Conf ] Douglas M. Grant , Jef L. van Meerbergen , Paul E. R. Lippens Optimization of Address Generator Hardware. [Citation Graph (0, 0)][DBLP ] Conf ] Ronn B. Brashear , Noel Menezes , Chanhee Oh , Lawrence T. Pillage , M. Ray Mercer Predicting Circuit Performance Using Circuit-level Statistical Timing Analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Mukund Sivaraman , Andrzej J. Strojwas Towards Incorporating Device Parameter Variations in Timing Analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Jürgen Frößl , Thomas Kropf A New Model to Uniformly Represent the Function and Timing of MOS Circuits and its Application to VHDL Simulation. [Citation Graph (0, 0)][DBLP ] Conf ] C. Safinia , Régis Leveugle , Gabriele Saucier Taking Advantage of High Level Functional Information to Refine Timing Analysis and Timing Modeling. [Citation Graph (0, 0)][DBLP ] Conf ] Rosa Rodríguez-Montañés , Joan Figueras Analysis of Bridging Defects in Sequential CMOS Circuits and their Current Testability. [Citation Graph (0, 0)][DBLP ] Conf ] Manoj Sachdev Transforming Sequential Logic in Digital CMOS ICs for Voltage and IDDQ Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Eugeni Isern , Joan Figueras Test of Bridging Faults in Scan-based Sequential Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Richard McGowen , F. Joel Ferguson A Study of Undetectable Non-Feedback Shorts for the Purpose of Physical-DFT. [Citation Graph (0, 0)][DBLP ] Conf ] Peter Vanbekbergen , Chantal Ykman-Couvreur , Bill Lin , Hugo De Man A Generalized Signal Transition Graph Model for Specification of Complex Interfaces. [Citation Graph (0, 0)][DBLP ] Conf ] Franz Korf , Rainer Schlör Interface Controller Synthesis from Requirement Specifications. [Citation Graph (0, 0)][DBLP ] Conf ] Sanjiv Narayan , Daniel Gajski Synthesis of System-Level Bus Interfaces. [Citation Graph (0, 0)][DBLP ] Conf ] Henrik Esbensen , Pinaki Mazumder A Genetic Algorithm for the Steiner Problem in a Graph. [Citation Graph (0, 0)][DBLP ] Conf ] Ed P. Huijbregts , Jos T. J. van Eijndhoven , Jochen A. G. Jess On Design Rule Correct Maze Routing. [Citation Graph (0, 0)][DBLP ] Conf ] Yu-Liang Wu , Malgorzata Marek-Sadowska An Efficient Router for 2-D Field Programmable Gate Arrays. [Citation Graph (0, 0)][DBLP ] Conf ] J. Akita , K. Asada A Method for Reducing Power Consumption of CMOS Logic Based on Signal Transition Probability. [Citation Graph (0, 0)][DBLP ] Conf ] How-Rern Lin , Ching-Lung Chou , Yu-Chin Hsu , TingTing Hwang Cell Height Driven Transistor Sizing in a Cell Based Module Design. [Citation Graph (0, 0)][DBLP ] Conf ] Bernard A. McCoy , Gabriel Robins Non-Tree Routing. [Citation Graph (0, 0)][DBLP ] Conf ] José T. de Sousa , Fernando M. Gonçalves , João Paulo Teixeira , Thomas W. Williams Fault Modeling and Defect Level Projections in Digital ICs. [Citation Graph (0, 0)][DBLP ] Conf ] Hua Xue , Chennian Di , Jochen A. G. Jess Probability Analysis for CMOS Floating Gate Faults. [Citation Graph (0, 0)][DBLP ] Conf ] Mohamed Jamoussi , Bozena Kaminska M-Testability: An Approach for Data-Path Testability Evaluation. [Citation Graph (0, 0)][DBLP ] Conf ] Daniel Gajski , Frank Vahid , Sanjiv Narayan A System-Design Methodology: Executable-Specification Refinement. [Citation Graph (0, 0)][DBLP ] Conf ] Tarek Ben Ismail , Kevin O'Brien , Ahmed Amine Jerraya Interactive System-level Partitioning with PARTIF. [Citation Graph (0, 0)][DBLP ] Conf ] Martyn Edwards , John Forrest A Development Environment for the Cosynthesis of Embedded Software/Hardware Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Jiro Naganuma , Takeshi Ogura , Tamio Hoshino High-Level Design Validation Using Algorithmic Debugging. [Citation Graph (0, 0)][DBLP ] Conf ] Bruno Rouzeyre , D. Dupont , G. Sagnes Component Selection, Scheduling and Control Schemes for High Level Synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] F. Depuydt , Werner Geurts , Gert Goossens , Hugo De Man Optimal Scheduling and Software Pipelining of Repetitive Signal Flow Graphs with Delay Line Optimization. [Citation Graph (0, 0)][DBLP ] Conf ] Jerry Chih-Yuan Yang , Giovanni De Micheli , Maurizio Damiani Scheduling with Environmental Constraints based on Automata Representations. [Citation Graph (0, 0)][DBLP ] Conf ] Koen Schoofs , Gert Goossens , Hugo De Man Signal Type Optimisation in the Design of Time-Multiplexed DSP Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Meng Chiy Lin , Jwu E. Chen , Chung-Len Lee TRANS: A Fast and Memory-Efficient Path Delay Fault Simulator. [Citation Graph (0, 0)][DBLP ] Conf ] Hannes C. Wittmann , Manfred Henftling Efficient Path Identification for Delay Testing - Time and Space Optimization. [Citation Graph (0, 0)][DBLP ] Conf ] D. Dumas , Patrick Girard , Christian Landrault , Serge Pravossoudovitch Effectiveness of a Variable Sampling Time Strategy for Delay Fault Diagnosis. [Citation Graph (0, 0)][DBLP ] Conf ] Arno Kunzmann , Frank Böhland Gate-Delay Fault Test with Conventional Scan-Design. [Citation Graph (0, 0)][DBLP ] Conf ] Stéphane Donnay , Koen Swings , Georges G. E. Gielen , Willy M. C. Sansen , Wim Kruiskamp , Domine Leenaerts A Methodology for Analog Design Automation in Mixed-Signal ASICs. [Citation Graph (0, 0)][DBLP ] Conf ] Vincent Moser , Pascal Nussbaum , Hans Peter Amann , Luc Astier , Fausto Pellandini A Graphical Approach to Analogue Behavioural Modelling. [Citation Graph (0, 0)][DBLP ] Conf ] Eamonn Byrne , Oliver McCarthy , David Lucas , Brian Donnellan An Overview of Analogue Optimisation Using "AD-OPT". [Citation Graph (0, 0)][DBLP ] Conf ] Makoto Ikeda , Kunihiro Asada A Reduced-swing Data Transmission Scheme for Resistive Bus Lines in VSLIs. [Citation Graph (0, 0)][DBLP ] Conf ] Yih-Lang Li , Cheng-Wen Wu Logic and Fault Simulation by Cellular Automata. [Citation Graph (0, 0)][DBLP ] Conf ] Kimon W. Michaels , Andrzej J. Strojwas Variable Accuracy Device Modeling for Event-Driven Circuit Simulation. [Citation Graph (0, 0)][DBLP ] Conf ] Jyh-Herng Wang , Jen-Teng Fan , Wu-Shiung Feng An Accurate Time-Domain Current Waveform Simulator for VLSI Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Zhihua Wang , Stephen W. Director An Efficient Yield Optimization Method Using A Two Step Linear Approximation of Circuit Performance. [Citation Graph (0, 0)][DBLP ] Conf ] Michael Nicolaidis , H. Bederr Efficient Implementations of Self-Checking Multiply and Divide Arrays. [Citation Graph (0, 0)][DBLP ] Conf ] Sybille Hellebrand , Hans-Joachim Wunderlich Synthesis of Self-Testable Controllers. [Citation Graph (0, 0)][DBLP ] Conf ] Taewhan Kim , Ki-Seok Chung , Chien-Liang Liu A Stepwise Refinement Data Path Synthesis Procedure for Easy Testability. [Citation Graph (0, 0)][DBLP ] Conf ] Marie-Lise Flottes , D. Hammad , Bruno Rouzeyre Automatic Synthesis of BISTed Data Paths From High Level Specification. [Citation Graph (0, 0)][DBLP ] Conf ] M. Straube , Wolfgang Wilkes , Gunter Schlageter HANDICAP - A System for Design Consulting. [Citation Graph (0, 0)][DBLP ] Conf ] Gunnar Bartels , Peter Kist , Kees Schot , Mattie Sim Flow Management Requirements of a Test Harness for Testing the Reliability of an Electronic CAD System. [Citation Graph (0, 0)][DBLP ] Conf ] Sandip Parikh , David Sarnoff , Michael L. Bushnell , James Sienicki , Ramakrishnan Ganesh Distributed Computing, Automatic Design, and Error Recovery in the ULYSSES II Framework. [Citation Graph (0, 0)][DBLP ] Conf ] Shih-Chieh Chang , David Ihsin Cheng , Malgorzata Marek-Sadowska Minimizing ROBDD Size of Incompletely Specified Multiple Output Functions. [Citation Graph (0, 0)][DBLP ] Conf ] R. Iris Bahar , Hyunwoo Cho , Gary D. Hachtel , Enrico Macii , Fabio Somenzi Timing Analysis of Combinational Circuits using ADD's. [Citation Graph (0, 0)][DBLP ] Conf ] Bernd Wurth , Norbert Wehn Efficient Calculation of Boolean Relations for Multi-Level Logic Optimization. [Citation Graph (0, 0)][DBLP ] Conf ] Paolo Camurati , Fulvio Corno , Paolo Prinetto , C. Bayol , B. Soulas System-Level Modeling and Verification: a Comprehensive Design Methodology. [Citation Graph (0, 0)][DBLP ] Conf ] Peter T. Breuer , Luis Sánchez Fernández , Carlos Delgado Kloos Clean formal semantics for VHDL. [Citation Graph (0, 0)][DBLP ] Conf ] Klaus Schneider , Thomas Kropf , Ramayya Kumar Control Path Oriented Verification of Sequential Generic Circuits with Control and Data Path. [Citation Graph (0, 0)][DBLP ] Conf ] N. M. Vitsyn The Russian EDA Standards Activities [Citation Graph (0, 0)][DBLP ] Conf ] Thomas Johansson , L. R. Virtanen , J. M. Gobbi ``Underground Capacitors'' Very Efficient Decoupling for High Performance UHF Signal Processing ICs. [Citation Graph (0, 0)][DBLP ] Conf ] Michel Robert , P. Gorria , Johel Mitéran , S. Turgis Design of a Real Time Geometric Classifier. [Citation Graph (0, 0)][DBLP ] Conf ] Alessandro Balboni , Claudio Costi , Franco Fummi , Donatella Sciuto From Behavioral Description to Systolic Array Based Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Abdessatar Abderrahman , Bozena Kaminska , Yvon Savaria Estimation of Simultaneous Switching Power and Ground Noise of Static CMOS Combinational Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] H. H. Ahmad , R. J. Mack AREAL: Automated Reasoning Expert for Analogue Layout. [Citation Graph (0, 0)][DBLP ] Conf ] Jean-Claude Dufourd , Jean-François Naviner An Optimizable Model for Process Independent Symbolic Design. [Citation Graph (0, 0)][DBLP ] Conf ] Wen Ching Wu , Chung-Len Lee , Jwu E. Chen , Won Yih Lin Distributed Fault Simulation for Sequential Circuits by Pattern Partitioning. [Citation Graph (0, 0)][DBLP ] Conf ] Wolfgang Vermeiren , Bernd Straube , Günter Elst A Suggestion for Accelerating the Analog Fault Simulation. [Citation Graph (0, 0)][DBLP ] Conf ] K. C. Koudakou Software Implementation and Statistical Optimization of Some Electronic Component's Lifetime. [Citation Graph (0, 0)][DBLP ] Conf ] Andrea Boni , G. Chiorboli , G. Franco , S. Mazzoleni , M. Ostacoli Physical Modeling of Linearity Errors for the Diagnosis of High Resolution R-2R D/A Converters. [Citation Graph (0, 0)][DBLP ] Conf ] Salman Ahmed , Peter Y. K. Cheung , Phil Collins A Model-based Approach to Analog Fault Diagnosis using Techniques from Optimisation. [Citation Graph (0, 0)][DBLP ] Conf ] A. J. van de Goor , Yervant Zorian , Ivo Schanstra Functional Tests for Ring-Address SRAM-type FIFOs. [Citation Graph (0, 0)][DBLP ] Conf ] Bernd Becker , Rolf Drechsler Testability of Circuits Derived from Functional Decision Diagrams. [Citation Graph (0, 0)][DBLP ] Conf ] M. Hirech , O. Florent , Alain Greiner , E. Rejouan A Redefinable Symbolic Simulation Technique to Testability Design Rules Checking. [Citation Graph (0, 0)][DBLP ] Conf ] Luc Burgun , N. Dictus , Alain Greiner , E. Pradho , C. Sarwary Multilevel Logic Synthesis of Very High Complexity Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Savita Banerjee , Rabindra K. Roy , Srimat T. Chakradhar , Dhiraj K. Pradhan Signal Transition Graph Transformations for Initializability. [Citation Graph (0, 0)][DBLP ] Conf ] Muhammad K. Dhodhi , Imtiaz Ahmad , C. Y. Roger Chen Synthesis of Application-Specific Multiprocessor Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Peter Zepter , Thorsten Grötker Generating Synchronous Timed Descriptions of Digital Receivers from Dynamic Data Flow System Level Configurations. [Citation Graph (0, 0)][DBLP ] Conf ] 