Conferences in DBLP
Sampling from the Multivariate Gaussian Distribution using Reconfigurable Hardware. [Citation Graph (, )][DBLP ] A Fast FPGA-Based 2-Opt Solver for Small-Scale Euclidean Traveling Salesman Problem. [Citation Graph (, )][DBLP ] On the Acceleration of Shortest Path Calculations in Transportation Networks. [Citation Graph (, )][DBLP ] Enhancing Relocatability of Partial Bitstreams for Run-Time Reconfiguration. [Citation Graph (, )][DBLP ] A Library and Platform for FPGA Bitstream Manipulation. [Citation Graph (, )][DBLP ] A Structural Object Programming Model, Architecture, Chip and Tools for Reconfigurable Computing. [Citation Graph (, )][DBLP ] Configurable Transactional Memory. [Citation Graph (, )][DBLP ] A Reconfigurable Hardware Interface for a Modern Computing System. [Citation Graph (, )][DBLP ] FPGA Acceleration of Gene Rearrangement Analysis. [Citation Graph (, )][DBLP ] FPGA-accelerated seed generation in Mercury BLASTP. [Citation Graph (, )][DBLP ] Systolic Architecture for Computational Fluid Dynamics on FPGAs. [Citation Graph (, )][DBLP ] FPGA-Based Multigrid Computation for Molecular Dynamics Simulations. [Citation Graph (, )][DBLP ] Reconfigurable Computing Cluster (RCC) Project: Investigating the Feasibility of FPGA-Based Petascale Computing. [Citation Graph (, )][DBLP ] Efficient Mapping of Dimensionality Reduction Designs onto Heterogeneous FPGAs. [Citation Graph (, )][DBLP ] K-means Clustering for Multispectral Images Using Floating-Point Divide. [Citation Graph (, )][DBLP ] Optimizing Logarithmic Arithmetic on FPGAs. [Citation Graph (, )][DBLP ] Generating FPGA-Accelerated DFT Libraries. [Citation Graph (, )][DBLP ] An FPGA implementation of pipelined multiplicative division with IEEE Rounding. [Citation Graph (, )][DBLP ] Integer Factorization Based on Elliptic Curve Method: Towards Better Exploitation of Reconfigurable Hardware. [Citation Graph (, )][DBLP ] Matched Filter Computation on FPGA, Cell and GPU. [Citation Graph (, )][DBLP ] A Data-Driven Approach for Pipelining Sequences of Data-Dependent Loops. [Citation Graph (, )][DBLP ] Writing Portable Applications that Dynamically Bind at Run Time to Reconfigurable Hardware. [Citation Graph (, )][DBLP ] Mitrion-C Application Development on SGI Altix 350/RC100. [Citation Graph (, )][DBLP ] Automatic On-chip Memory Minimization for Data Reuse. [Citation Graph (, )][DBLP ] Scientific Application Acceleration with Reconfigurable Functional Units. [Citation Graph (, )][DBLP ] Design and Implementation of a Highly Parameterised FPGA-Based Skeleton for Pairwise Biological Sequence Alignment. [Citation Graph (, )][DBLP ] The Case for Dynamic Execution on Dynamic Hardware. [Citation Graph (, )][DBLP ] On Solving RC5 Challenges with FPGAs. [Citation Graph (, )][DBLP ] Operating System Integration and Performance of a Multi Stream Cipher Architecture for Reconfigurable System-on-Chip. [Citation Graph (, )][DBLP ] A Novel Technique to Create Energy-Efficient Contexts for Reconfigurable Logic. [Citation Graph (, )][DBLP ] New Protection Mechanisms for Intellectual Property in Reconfigurable Logic. [Citation Graph (, )][DBLP ] Establishing Chain of Trust in Reconfigurable Hardware. [Citation Graph (, )][DBLP ] Hand-based Interface for Augmented Reality. [Citation Graph (, )][DBLP ] Discrete-Time Cellular Neural Networks in FPGA. [Citation Graph (, )][DBLP ] Run-time mapping and communication strategies for Homogeneous NoC-Based MPSoCs. [Citation Graph (, )][DBLP ] Code Compressor and Decompressor for Ultra Large Instruction Width Coarse-Grain Reconfigurable Systems. [Citation Graph (, )][DBLP ] Software/Hardware Co-Scheduling for Reconfigurable Computing Systems. [Citation Graph (, )][DBLP ] Mapping Real Time Operating System on Reconfigurable Instruction Cell Based Architectures. [Citation Graph (, )][DBLP ] Abstracting Modern FCCMs To Provide a Single Interface to Architectural Resources. [Citation Graph (, )][DBLP ] A Novel Technique to Create Energy-Efficient Contexts for Reconfigurable Logic. [Citation Graph (, )][DBLP ] Heterogeneous Floorplanner for FPGA. [Citation Graph (, )][DBLP ] Automatic Self-Reconfiguration of System-on-Chip Peripherals. [Citation Graph (, )][DBLP ] A Hybrid Memory Sub-system for Video Coding Applications. [Citation Graph (, )][DBLP ] Rapid Prototyping of Large-scale Analog Circuits With Field Programmable Analog Array. [Citation Graph (, )][DBLP ] PixelStreams-based implementation of videodetector. [Citation Graph (, )][DBLP ] Design Space Exploration for the BLAST Algorithm Implementation. [Citation Graph (, )][DBLP ] An Integrated Video Compression, Encryption and Information Hiding Architecture based on the SCAN Algorithm and the Stretch Technology. [Citation Graph (, )][DBLP ] A Configurable Processor Synthesis System. [Citation Graph (, )][DBLP ] Low-Cost Stereo Vision on an FPGA. [Citation Graph (, )][DBLP ] Methodology and Experimental Setup for the Determination of System-level Dynamic Reconfiguration Overhead. [Citation Graph (, )][DBLP ] Quantifying Effective Memory Bandwidth of Platform FPGAs. [Citation Graph (, )][DBLP ] A Flexible Filter Processor for Fading Channel Simulation. [Citation Graph (, )][DBLP ] RBoot: Software Infrastructure for a Remote FPGA Laboratory. [Citation Graph (, )][DBLP ] Jumble: A Hardware-in-the-Loop Simulation System for JHDL. [Citation Graph (, )][DBLP ] Sparse Matrix-Vector Multiplication Design on FPGAs. [Citation Graph (, )][DBLP ] Changing Output Quality for Thermal Management. [Citation Graph (, )][DBLP ] Hardware/Software co-design of a key point detector on FPGA. [Citation Graph (, )][DBLP ] 