Conferences in DBLP

Symposium on Field Programmable Gate Arrays (FPGA) (fpga)
2008 (conf/fpga/2008)

1. 
   Designing with extreme parallelism. [Citation Graph (, )][DBLP]
   
   
2. 
   Architecture-specific packing for virtex-5 FPGAs. [Citation Graph (, )][DBLP]
   
   
3. 
   High-quality, deterministic parallel placement for FPGAs on commodity hardware. [Citation Graph (, )][DBLP]
   
   
4. 
   Enforcing long-path timing closure for FPGA routing with path searches on clamped lexicographic spirals. [Citation Graph (, )][DBLP]
   
   
5. 
   Beyond the arithmetic constraint: depth-optimal mapping of logic chains in LUT-based FPGAs. [Citation Graph (, )][DBLP]
   
   
6. 
   WireMap: FPGA technology mapping for improved routability. [Citation Graph (, )][DBLP]
   
   
7. 
   Mapping for better than worst-case delays in LUT-based FPGA designs. [Citation Graph (, )][DBLP]
   
   
8. 
   Lithographic aerial image simulation with FPGA-based hardwareacceleration. [Citation Graph (, )][DBLP]
   
   
9. 
   A complexity-effective architecture for accelerating full-system multiprocessor simulations using FPGAs. [Citation Graph (, )][DBLP]
   
   
10. 
    A-Ports: an efficient abstraction for cycle-accurate performance models on FPGAs. [Citation Graph (, )][DBLP]
    
    
11. 
    Efficient ASIP design for configurable processors with fine-grained resource sharing. [Citation Graph (, )][DBLP]
    
    
12. 
    Pattern-based behavior synthesis for FPGA resource reduction. [Citation Graph (, )][DBLP]
    
    
13. 
    C is for circuits: capturing FPGA circuits as sequential code for portability. [Citation Graph (, )][DBLP]
    
    
14. 
    Extreme parallel architectures for the masses. [Citation Graph (, )][DBLP]
    
    
15. 
    TORCH: a design tool for routing channel segmentation in FPGAs. [Citation Graph (, )][DBLP]
    
    
16. 
    Modeling routing demand for early-stage FPGA architecture development. [Citation Graph (, )][DBLP]
    
    
17. 
    Area and delay trade-offs in the circuit and architecture design of FPGAs. [Citation Graph (, )][DBLP]
    
    
18. 
    Trace-based framework for concurrent development of process and FPGA architecture considering process variation and reliability. [Citation Graph (, )][DBLP]
    
    
19. 
    A novel FPGA logic block for improved arithmetic performance. [Citation Graph (, )][DBLP]
    
    
20. 
    Architectural improvements for field programmable counter arrays: enabling efficient synthesis of fast compressor trees on FPGAs. [Citation Graph (, )][DBLP]
    
    
21. 
    The amorphous FPGA architecture. [Citation Graph (, )][DBLP]
    
    
22. 
    Reconfigurable computing for learning Bayesian networks. [Citation Graph (, )][DBLP]
    
    
23. 
    HybridOS: runtime support for reconfigurable accelerators. [Citation Graph (, )][DBLP]
    
    
24. 
    Vector processing as a soft-core CPU accelerator. [Citation Graph (, )][DBLP]
    
    
25. 
    FPGA-optimised high-quality uniform random number generators. [Citation Graph (, )][DBLP]
    
    
26. 
    A hardware framework for the fast generation of multiple long-period random number streams. [Citation Graph (, )][DBLP]
    
    
27. 
    FPGA interconnect design using logical effort. [Citation Graph (, )][DBLP]
    
    
28. 
    Efficient tiling patterns for reconfigurable gate arrays. [Citation Graph (, )][DBLP]
    
    
29. 
    Speed and yield enhancement by track swapping on critical paths utilizing random variations for FPGAs. [Citation Graph (, )][DBLP]
    
    
30. 
    Measuring and modeling FPGA clock variability. [Citation Graph (, )][DBLP]
    
    
31. 
    High-throughput interconnect wave-pipelining for global communication in FPGAs. [Citation Graph (, )][DBLP]
    
    
32. 
    A type system for static typing of a domain-specific language. [Citation Graph (, )][DBLP]
    
    
33. 
    Configurable decoders with application in fast partial reconfiguration of FPGAs. [Citation Graph (, )][DBLP]
    
    
34. 
    When FPGAs are better at floating-point than microprocessors. [Citation Graph (, )][DBLP]
    
    
35. 
    An integrated debugging environment for FPGA computing platforms. [Citation Graph (, )][DBLP]
    
    
36. 
    Efficient FPGA implementation of qr decomposition using a systolic array architecture. [Citation Graph (, )][DBLP]
    
    
37. 
    Retrieving 3-d information with FPGA-based stream processing. [Citation Graph (, )][DBLP]
    
    
38. 
    CHiMPS: a high-level compilation flow for hybrid CPU-FPGA architectures. [Citation Graph (, )][DBLP]
    
    
39. 
    Communication bottleneck in hardware-software partitioning. [Citation Graph (, )][DBLP]
    
    
40. 
    FPGA implementation of a novel algorithm for on-line bar breakage detection on induction motors. [Citation Graph (, )][DBLP]
    
    
41. 
    FPGA based multiple-channel vibration analyzer for industrial applications with reconfigurable post-processing capabilities for automatic failure detection on machinery. [Citation Graph (, )][DBLP]
    
    
42. 
    A pipelined binary tree as a case study on designing efficient circuits for an FPGA in a bram aware design. [Citation Graph (, )][DBLP]
    
    
43. 
    Implementing high-speed string matching hardware for network intrusion detection systems. [Citation Graph (, )][DBLP]
    
    
44. 
    From the bitstream to the netlist. [Citation Graph (, )][DBLP]
    
    
45. 
    Fpga-based data acquisition system for a positron emission tomography (PET) scanner. [Citation Graph (, )][DBLP]
    
    
46. 
    Flexible FPGA-based parallel architecture for identification of repetitive sequences in interleaved pulse trains. [Citation Graph (, )][DBLP]