Conferences in DBLP

Symposium on Field Programmable Gate Arrays (FPGA) (fpga)
2010 (conf/fpga/2010)

1. 
   FPGA-2010 pre-conference workshop on open-source for FPGA. [Citation Graph (, )][DBLP]
   
   
2. 
   Intel nehalem processor core made FPGA synthesizable. [Citation Graph (, )][DBLP]
   
   
3. 
   FPGA prototyping of an amba-based windows-compatible SoC. [Citation Graph (, )][DBLP]
   
   
4. 
   Predicting the performance of application-specific NoCs implemented on FPGAs. [Citation Graph (, )][DBLP]
   
   
5. 
   Combining multicore and reconfigurable instruction set extensions. [Citation Graph (, )][DBLP]
   
   
6. 
   Energy efficient sensor node implementations. [Citation Graph (, )][DBLP]
   
   
7. 
   Efficient multi-ported memories for FPGAs. [Citation Graph (, )][DBLP]
   
   
8. 
   Automatic generation of high-performance multipliers for FPGAs with asymmetric multiplier blocks. [Citation Graph (, )][DBLP]
   
   
9. 
   Bit-level optimization for high-level synthesis and FPGA-based acceleration. [Citation Graph (, )][DBLP]
   
   
10. 
    Designing hardware with dynamic memory abstraction. [Citation Graph (, )][DBLP]
    
    
11. 
    High-throughput bayesian computing machine with reconfigurable hardware. [Citation Graph (, )][DBLP]
    
    
12. 
    High throughput and large capacity pipelined dynamic search tree on FPGA. [Citation Graph (, )][DBLP]
    
    
13. 
    FPMR: MapReduce framework on FPGA. [Citation Graph (, )][DBLP]
    
    
14. 
    Acceleration of an analytical approach to collateralized debt obligation pricing. [Citation Graph (, )][DBLP]
    
    
15. 
    A 3d-audio reconfigurable processor. [Citation Graph (, )][DBLP]
    
    
16. 
    Accelerating Monte Carlo based SSTA using FPGA. [Citation Graph (, )][DBLP]
    
    
17. 
    Axel: a heterogeneous cluster with FPGAs and GPUs. [Citation Graph (, )][DBLP]
    
    
18. 
    Server-side coprocessor updating for mobile devices with FPGAs. [Citation Graph (, )][DBLP]
    
    
19. 
    Accurately evaluating application performance in simulated hybrid multi-tasking systems. [Citation Graph (, )][DBLP]
    
    
20. 
    Programming high performance signal processing systems in high level languages. [Citation Graph (, )][DBLP]
    
    
21. 
    Towards scalable placement for FPGAs. [Citation Graph (, )][DBLP]
    
    
22. 
    FPGA power reduction by guarded evaluation. [Citation Graph (, )][DBLP]
    
    
23. 
    A comprehensive approach to modeling, characterizing and optimizing for metastability in FPGAs. [Citation Graph (, )][DBLP]
    
    
24. 
    Variation-aware placement for FPGAs with multi-cycle statistical timing analysis. [Citation Graph (, )][DBLP]
    
    
25. 
    Global delay optimization using structural choices. [Citation Graph (, )][DBLP]
    
    
26. 
    Building a faster boolean matcher using bloom filter. [Citation Graph (, )][DBLP]
    
    
27. 
    Haptic rendering of deformable objects using a multiple FPGA parallel computing architecture. [Citation Graph (, )][DBLP]
    
    
28. 
    A 1 cycle-per-byte XML parsing accelerator. [Citation Graph (, )][DBLP]
    
    
29. 
    A modular NFA architecture for regular expression matching. [Citation Graph (, )][DBLP]
    
    
30. 
    Scalable network virtualization using FPGAs. [Citation Graph (, )][DBLP]
    
    
31. 
    Degradation in FPGAs: measurement and modelling. [Citation Graph (, )][DBLP]
    
    
32. 
    On-line sensing for healthier FPGA systems. [Citation Graph (, )][DBLP]
    
    
33. 
    Voter insertion algorithms for FPGA designs using triple modular redundancy. [Citation Graph (, )][DBLP]
    
    
34. 
    Maximizing area-constrained partial fault tolerance in reconfigurable logic. [Citation Graph (, )][DBLP]
    
    
35. 
    The impact of interconnect architecture on via-programmed structured ASICs (VPSAs). [Citation Graph (, )][DBLP]
    
    
36. 
    Efficient FPGAs using nanoelectromechanical relays. [Citation Graph (, )][DBLP]
    
    
37. 
    Towards 5ps resolution TDC on a dynamically reconfigurable FPGA (abstract only). [Citation Graph (, )][DBLP]
    
    
38. 
    A multi-FPGA based platform for emulating a 100m-transistor-scale processor with high-speed peripherals (abstract only). [Citation Graph (, )][DBLP]
    
    
39. 
    An architecture for graphics processing in an FPGA (abstract only). [Citation Graph (, )][DBLP]
    
    
40. 
    Application of a reconfigurable computing cluster to ultra high throughput genome resequencing (abstract only). [Citation Graph (, )][DBLP]
    
    
41. 
    FPGA implementation of highly parallelized decoder logic for network coding (abstract only). [Citation Graph (, )][DBLP]
    
    
42. 
    FPGA based chip emulation system for test development and verification of analog and mixed signal circuits (abstract only). [Citation Graph (, )][DBLP]
    
    
43. 
    Memory efficient string matching: a modular approach on FPGAs (abstract only). [Citation Graph (, )][DBLP]
    
    
44. 
    LambdaRank acceleration for relevance ranking in web search engines (abstract only). [Citation Graph (, )][DBLP]
    
    
45. 
    Implementing dynamic information flow tracking on microprocessors with integrated FPGA fabric (abstract only). [Citation Graph (, )][DBLP]
    
    
46. 
    Design space exploration of throughput-optimized arrays from recurrence abstractions (abstract only). [Citation Graph (, )][DBLP]
    
    
47. 
    A semi-automatic toolchain for reconfigurable multiprocessor systems-on-chip: architecture development and application partitioning (abstract only). [Citation Graph (, )][DBLP]
    
    
48. 
    A dependency graph based methodology for parallelizing HLL applications on FPGA (abstract only). [Citation Graph (, )][DBLP]
    
    
49. 
    Reconfigurable custom floating-point instructions (abstract only). [Citation Graph (, )][DBLP]
    
    
50. 
    Multiplier architectures for FPGA double precision functions (abstract only). [Citation Graph (, )][DBLP]
    
    
51. 
    Automatic tool flow for shift-register-LUT reconfiguration: making run-time reconfiguration fast and easy (abstract only). [Citation Graph (, )][DBLP]
    
    
52. 
    Odin II: an open-source verilog HDL synthesis tool for FPGA cad flows (abstract only). [Citation Graph (, )][DBLP]
    
    
53. 
    Aggressive overclocking support using a novel timing error recovery technique on FPGAs (abstract only). [Citation Graph (, )][DBLP]
    
    
54. 
    LUT-based FPGA technology mapping for reliability (abstract only). [Citation Graph (, )][DBLP]
    
    
55. 
    A heuristic algorithm for LUT-based FPGA technology mapping using the lower bound for DAG covering problem (abstract only). [Citation Graph (, )][DBLP]
    
    
56. 
    Scalable architecture for programmable quantum gate array (abstract only). [Citation Graph (, )][DBLP]
    
    
57. 
    Fine-grained vs. coarse-grained shift-and-add arithmetic in FPGAs (abstract only). [Citation Graph (, )][DBLP]
    
    
58. 
    Heterogeneous-ASIF: an application specific inflexible FPGA using heterogeneous logic blocks (abstract only). [Citation Graph (, )][DBLP]
    
    
59. 
    DRAM-based FPGA enabled by three-dimensional (3d) memory stacking (abstract only). [Citation Graph (, )][DBLP]
    
    
60. 
    Nano-magnetic non-volatile CMOS circuits for nano-scale FPGAs (abstract only). [Citation Graph (, )][DBLP]
    
    
61. 
    High-performance FPGA based on novel DSS-MOSFET and non-volatile configuration memory (abstract only). [Citation Graph (, )][DBLP]
    
    
62. 
    Modeling and simulation of nano quantum FPGAs (abstract only). [Citation Graph (, )][DBLP]
    
    
63. 
    Energy reduction with run-time partial reconfiguration (abstract only). [Citation Graph (, )][DBLP]
    
    
64. 
    Design and evaluation of a parameterizable NoC router for FPGAs (abstract only). [Citation Graph (, )][DBLP]
    
    
65. 
    Minimizing partial reconfiguration overhead with fully streaming DMA engines and intelligent ICAP controller (abstract only). [Citation Graph (, )][DBLP]
    
    
66. 
    FPGA-based prototyping of a 2D MESH / TORUS on-chip interconnect (abstract only). [Citation Graph (, )][DBLP]