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Conferences in DBLP

Field-Programmable Logic and Applications (FPL) (fpl)
2007 (conf/fpl/2007)


  1. The Intel Geneseo Project. [Citation Graph (, )][DBLP]


  2. System-Level Design for FPGAs. [Citation Graph (, )][DBLP]


  3. Adventures with a Reconfigurable Research Platform. [Citation Graph (, )][DBLP]


  4. Redefining the FPGA for the Next Generation. [Citation Graph (, )][DBLP]


  5. Design Space Exploration of the European Option Benchmark Using HyperStreams. [Citation Graph (, )][DBLP]


  6. Accelerating a Medical 3D Brain MRI Analysis Algorithm using a High-Performance Reconfigurable Computer. [Citation Graph (, )][DBLP]


  7. Soft-Hard 3D FD-TD Solver for Non Destructive Evaluation. [Citation Graph (, )][DBLP]


  8. Array Synthesis in SystemC Hardware Compilation. [Citation Graph (, )][DBLP]


  9. Floating-Point Trigonometric Functions for FPGAs. [Citation Graph (, )][DBLP]


  10. A Method for Fast Hardware Specialization at run-time. [Citation Graph (, )][DBLP]


  11. A Many-core Implementation based on the Reconfigurable Mesh Model. [Citation Graph (, )][DBLP]


  12. An FPGA Approach to Quantifying Coherence Traffic Efficiency on Multiprocessor Systems. [Citation Graph (, )][DBLP]


  13. RAMP Blue: A Message-Passing Manycore System in FPGAs. [Citation Graph (, )][DBLP]


  14. A Radio Astronomy Correlator Optimized for the XILINX VIRTEX-4 SX FPGA. [Citation Graph (, )][DBLP]


  15. TANOR: A Tool for Accelerating N-Body Simulations on Reconfigurable Platforms. [Citation Graph (, )][DBLP]


  16. Performance Modeling of 2D Cellular Automata on FPGA. [Citation Graph (, )][DBLP]


  17. Bringing High-Performance Reconfigurable Computing to Exact Computations. [Citation Graph (, )][DBLP]


  18. Applying Out-of-Core QR Decomposition Algorithms on FPGA-Based Systems. [Citation Graph (, )][DBLP]


  19. Multi-processor System-level Synthesis for Multiple Applications on Platform FPGA. [Citation Graph (, )][DBLP]


  20. Supporting High Level Language Semantics Within Hardware Resident Threads. [Citation Graph (, )][DBLP]


  21. Formal Modeling of Process Migration. [Citation Graph (, )][DBLP]


  22. Dynamic Cache Switching in Reconfigurable Embedded Systems. [Citation Graph (, )][DBLP]


  23. Improving Timing-Driven FPGA Packing With Physical Information. [Citation Graph (, )][DBLP]


  24. Clock-Aware Placement for FPGAs. [Citation Graph (, )][DBLP]


  25. Fast On-line Task Placement and Scheduling on Reconfigurable Devices. [Citation Graph (, )][DBLP]


  26. A Hardware Algorithm for the Minimum p-Quasi Clique Cover Problem. [Citation Graph (, )][DBLP]


  27. High speed tablation system using an FPGA designed for distribution tables of frequent DNA subsequences. [Citation Graph (, )][DBLP]


  28. Discrete Event Simulation of Molecular Dynamics with Configurable Logic. [Citation Graph (, )][DBLP]


  29. Pre-route Interconnect Capacitance and Power Estimation in FPGAs. [Citation Graph (, )][DBLP]


  30. Exploiting Hardware and Software Low Power Techniques for Energy Efficient Co-scheduling in Dynamically Reconfigurable Systems. [Citation Graph (, )][DBLP]


  31. A Power Estimation Model for an FPGA-based Softcore Processor. [Citation Graph (, )][DBLP]


  32. A Software Defined Radio Application Utilizing Modern FPGAs and NoC Interconnects. [Citation Graph (, )][DBLP]


  33. Intellectual Property Protection of HDL IP Cores Through Automated Sognature Hosting. [Citation Graph (, )][DBLP]


  34. Physical Unclonable Functions, FPGAs and Public-Key Crypto for IP Protection. [Citation Graph (, )][DBLP]


  35. Domain-Specific Hybrid FPGA: Architecture and Floating Point Applications. [Citation Graph (, )][DBLP]


  36. Embedded Programmable Logic Core Enhancements for System Bus Interfaces. [Citation Graph (, )][DBLP]


  37. Improving Pipelined Soft Processors with Multithreading. [Citation Graph (, )][DBLP]


  38. An area-efficient alternative to adaptive median filtering in FPGAs. [Citation Graph (, )][DBLP]


  39. An Efficient Implementation of a 2D DWT on FPGA. [Citation Graph (, )][DBLP]


  40. H.264/AVC In-Loop De-Blocking Filter Targeting a Dynamically Reconfigurable Instruction Cell Based Architecture. [Citation Graph (, )][DBLP]


  41. On the feasibility of early routing capacitance estimation for FPGAs. [Citation Graph (, )][DBLP]


  42. Power Reduction in Network Equipment through Adaptive Partial Reconfiguration. [Citation Graph (, )][DBLP]


  43. Adaptive Thermoregulation for Applications on Reconfigurable Devices. [Citation Graph (, )][DBLP]


  44. FPGA Implementation of a Data-Driven Stochastic Biochemical Simulator with the Next Reaction Method. [Citation Graph (, )][DBLP]


  45. GENDIV - A Hardware Algorithm for Intron and Exon String Detection in DNA Chains. [Citation Graph (, )][DBLP]


  46. A Unified Streaming Architecture for Real Time Face Detection and Gender Classification. [Citation Graph (, )][DBLP]


  47. Disjoint Pattern Enumeration for Custom Instructions Identification. [Citation Graph (, )][DBLP]


  48. Fast and Accurate Interval-Based Timing Estimator for Variability-Aware FPGA Physical Synthesis Tools. [Citation Graph (, )][DBLP]


  49. An Execution Model for Hardware/Software Compilation and its System-Level Realization. [Citation Graph (, )][DBLP]


  50. Module Graph Merging and Placement to Reduce Reconfiguration Overheads in Paged FPGA Devices. [Citation Graph (, )][DBLP]


  51. Layered Approach to Instrinsic Evolvable Hardware Using Direct Bistream Manipulation of VIRTEX II Pro Devices. [Citation Graph (, )][DBLP]


  52. A generalized and unified SPFD-based rewiring technique. [Citation Graph (, )][DBLP]


  53. Improving External Memory Access for Avalon Systems on Programmable Chips.. [Citation Graph (, )][DBLP]


  54. Time Predictable CPU and DMA Shared Memory Access. [Citation Graph (, )][DBLP]


  55. Virtualization on the Tartan Reconfigurable Architecture. [Citation Graph (, )][DBLP]


  56. A Design Methodology for Communication Infrastructures on Partially Reconfigurable FPGAs. [Citation Graph (, )][DBLP]


  57. Efficient FPGA-based multipliers for F_3^97 and F_3^(6*97). [Citation Graph (, )][DBLP]


  58. Efficient mapping of a Kalman filter into an FPGA using Taylor Expansion. [Citation Graph (, )][DBLP]


  59. Implementation of a Virtual Internal Configuration Access Port (JCAP) for Enabling Partial Self-Reconfiguration on Xilinx Spartan III FPGAs. [Citation Graph (, )][DBLP]


  60. L4: An FPGA-Based Accelerator for Detailed Maze Routing. [Citation Graph (, )][DBLP]


  61. Improving Annealing Via Directed Moves. [Citation Graph (, )][DBLP]


  62. artNoC - A Novel Multi-Functional Router Architecture for Organic Computing. [Citation Graph (, )][DBLP]


  63. A Time-Triggered Network-on-Chip. [Citation Graph (, )][DBLP]


  64. A Temporal Correlation Based Port Combination Methodology for Networks-on-chip on Reconfigurable Systems. [Citation Graph (, )][DBLP]


  65. Router Design for Application Specific Networks-on-Chip on Reconfigurable Systems. [Citation Graph (, )][DBLP]


  66. The ANDRES Project: Analysis and Design of Run-Time Reconfigurable, Heterogeneous Systems. [Citation Graph (, )][DBLP]


  67. HARTES Toolchain Early Evaluation: Profiling, Compilation and HDL Generation. [Citation Graph (, )][DBLP]


  68. MORPHEUS: Heterogeneous Reconfigurable Computing. [Citation Graph (, )][DBLP]


  69. On-line Routing of Reconfigurable Functions for Future Self-Adaptive Systems - Investigations within the ÆTHER Project. [Citation Graph (, )][DBLP]


  70. Equivalence Verification of FPGA and Structured ASIC Implementations. [Citation Graph (, )][DBLP]


  71. Statistical Generic And Chip-Specific Skew Assignment for Improving Timing Yield of FPGAs. [Citation Graph (, )][DBLP]


  72. Fault Models and Yield Analysis for QCA-based PLAs. [Citation Graph (, )][DBLP]


  73. ReconOS: An RTOS supporting Hard- and Software Threads. [Citation Graph (, )][DBLP]


  74. The Design of Multitasking Based Applications on Reconfigurable Instruction Cell Bsed Architectures. [Citation Graph (, )][DBLP]


  75. Monte Carlo Logarithmic Number System for Model Predictive Control. [Citation Graph (, )][DBLP]


  76. Dynamic Voltage Scaling in a FPGA-based System-on-Chip. [Citation Graph (, )][DBLP]


  77. Multiplexer-based routing fabric for reconfigurable logic. [Citation Graph (, )][DBLP]


  78. H.264 Decoder at HD Resolution on a Coarse Grain Dynamically Reconfigurable Architecture. [Citation Graph (, )][DBLP]


  79. Implementation on FPGA of a LUT-based atan(Y/X) operator suitable for Synchronization Algorithms. [Citation Graph (, )][DBLP]


  80. Efficient Priority-Queue Data Structure for Hardware Implementation. [Citation Graph (, )][DBLP]


  81. Compact AES-based Architecture for Symmetric Encryption, Hash Function, and Random Number Generation. [Citation Graph (, )][DBLP]


  82. Design of a hardware accelerator for fingerprint alignment. [Citation Graph (, )][DBLP]


  83. An FPGA Implementation of Multiple Sequence Alignment Based on Carrillo-Lipman Method. [Citation Graph (, )][DBLP]


  84. An FPGA Solver for Very Large SAT Problems. [Citation Graph (, )][DBLP]


  85. A Multi Objective GA based Physical Placement Algorithm for Heterogeneous Dynamically Reconfigurable Arrays. [Citation Graph (, )][DBLP]


  86. Aggressive Loop Pipelining for Reconfigurable Architectures. [Citation Graph (, )][DBLP]


  87. Comrade - A Compiler for Adaptive Computing Systems Using a Novel Fast Speculation Technique. [Citation Graph (, )][DBLP]


  88. Self-Healing Circuits for Space-Applications. [Citation Graph (, )][DBLP]


  89. Automatic Software Hardware Co-Design for Reconfigurable Computing Systems. [Citation Graph (, )][DBLP]


  90. VPH - A Tool for Exploring Hybrid FPGAs. [Citation Graph (, )][DBLP]


  91. Hybridthreads Compiler: Generation of Application Specific Hardware Thread Cores from C. [Citation Graph (, )][DBLP]


  92. Wires On Demand: Run-Time Communication Synthesis for Reconfigurable Computing. [Citation Graph (, )][DBLP]


  93. A Behavioral Synthesis Approach for Distributed Memory FPGA Architectures. [Citation Graph (, )][DBLP]


  94. Mapping A VLIWxSIMD Processor on an FPGA: Scalability and Performance. [Citation Graph (, )][DBLP]


  95. An Automatic Compilation Framework for Configurable Architectures. [Citation Graph (, )][DBLP]


  96. A high throughput area time efficient pseudo uniform random number generator based on the TT800 algorithm. [Citation Graph (, )][DBLP]


  97. Dynamic Partial FPGA Reconfiguration in a Prototype Microprocessor System. [Citation Graph (, )][DBLP]


  98. A Load/Store Unit for a Memcpy Hardware Accelerator. [Citation Graph (, )][DBLP]


  99. Incremental Fault Emulation. [Citation Graph (, )][DBLP]


  100. A novel motion estimation power reduction technique. [Citation Graph (, )][DBLP]


  101. A Variable Grain Logic Cell Architecture for Reconfigurable Logic Cores. [Citation Graph (, )][DBLP]


  102. A High Speed License Plate Recognition System on an FPGA. [Citation Graph (, )][DBLP]


  103. REDEFINE: Architecture of a SoC Fabric for Runtime Composition of Computation Structures. [Citation Graph (, )][DBLP]


  104. Implementation of a 2-D 8x8 IDCT on the Reconfigurable Montium Core. [Citation Graph (, )][DBLP]


  105. A Reprogrammable and Scalable Multimedia Traffic Generator/Monitor on FPGA. [Citation Graph (, )][DBLP]


  106. C++ based design flow for reconfigurable image processing systems. [Citation Graph (, )][DBLP]


  107. A floating-point Extended Kalman Filter implementation for autonomous mobile robots. [Citation Graph (, )][DBLP]


  108. Efficient External Memory Interface for Multi-processor Platforms Realized on FPGA Chips. [Citation Graph (, )][DBLP]


  109. Hardware/Software Process Migration and RTL Simulation. [Citation Graph (, )][DBLP]


  110. Implementation of a barotropic operator for ocean model simulation using a reconfigurable machine. [Citation Graph (, )][DBLP]


  111. Evolutionary Search Applied to Reconfigurable Analogue Control. [Citation Graph (, )][DBLP]


  112. Soft IP core implementation of recursive least squares filter using only multplicative and additive operators. [Citation Graph (, )][DBLP]


  113. Characterizing Effective Memory Bandwidth of Designs with Concurrent High-Performance Computing Cores. [Citation Graph (, )][DBLP]


  114. A Design Flow to Map Parallel Applications onto FPGAs. [Citation Graph (, )][DBLP]


  115. A Hybrid Reconfigurable Cluster-on-Chip Architecture With Message Passing Interface For Image Processing Applications. [Citation Graph (, )][DBLP]


  116. Novel Multi-Layer floorplanning for Heterogeneous FPGAs. [Citation Graph (, )][DBLP]


  117. Automatic Accuracy-Guaranteed Bit-Width Optimization for Fixed and Floating-Point Systems. [Citation Graph (, )][DBLP]


  118. Accelerating Microblaze Floating Point Operations. [Citation Graph (, )][DBLP]


  119. Analysis of Kernel Effects on Optimisation Mismatch in Cache Reconfiguration. [Citation Graph (, )][DBLP]


  120. High Level Power Optimization by Type Inference on the Generation of Application Specific Circuits on FPGAs. [Citation Graph (, )][DBLP]


  121. Dynamically reconfigurable dataflow architecture for high-performance digital signal processing on multi-FPGA platforms. [Citation Graph (, )][DBLP]


  122. RIC Fast Adder and its Set Tolerant Implementation in FPGAs. [Citation Graph (, )][DBLP]


  123. Solving RC5 Challenges with Hardware -- a Distributed.net Perspective --. [Citation Graph (, )][DBLP]


  124. High Level Abstraction Language as an Alternative to Embedded Processors for Internet Packet Processing in FPGA. [Citation Graph (, )][DBLP]


  125. Exploring Alternative 3D FPGA Architectures: Design Methodology and CAD Tool Support. [Citation Graph (, )][DBLP]


  126. AdaBoost Engine. [Citation Graph (, )][DBLP]


  127. An FPGA Based Memory Efficient Shared Buffer Implementation. [Citation Graph (, )][DBLP]


  128. Efficient Modeling and Floorplanning of Embedded-FPGA Fabric. [Citation Graph (, )][DBLP]


  129. A New Scalable Hardware Architecture for RSA Algorithm. [Citation Graph (, )][DBLP]


  130. Implementation of Low Frequency Finite State Machines Using the VIRTEX SRL16 Primitive. [Citation Graph (, )][DBLP]


  131. Run-time Partial Reconfiguration for Removal, Placement and Routing on the Virtex-II-Pro. [Citation Graph (, )][DBLP]


  132. Dynamic reconfiguration management based on a distributed object model. [Citation Graph (, )][DBLP]


  133. Circuit Switched Run-Time Adaptive Network-on-Chip for Image Processing Applications. [Citation Graph (, )][DBLP]


  134. An OCM based shared Memory controller for Virtex 4. [Citation Graph (, )][DBLP]


  135. DWARV: DelftWorkBench Automated Reconfigurable VHDL Generator. [Citation Graph (, )][DBLP]


  136. Accelerating tool path computing in CAD/CAM: A FPGA architecture for turning lathe machining.. [Citation Graph (, )][DBLP]


  137. Exploiting Analog and Digital Reconfiguration for Smart Sensor Interfacing. [Citation Graph (, )][DBLP]


  138. SoPC architecture for a Key Point Detector. [Citation Graph (, )][DBLP]


  139. A Pipeline Implementation of a Watershed Algorithm on FPGA. [Citation Graph (, )][DBLP]


  140. FPGA Implementation of 64-bit Exponential Function for HPC. [Citation Graph (, )][DBLP]


  141. A Graphical Model-Level Debugger for Heterogenous Reconfigurable Architectures. [Citation Graph (, )][DBLP]


  142. A Run-time Reconfigurable Processor for Video Motion Estimation. [Citation Graph (, )][DBLP]


  143. Confiuartion Management in the Context of Self Adapative Systems. [Citation Graph (, )][DBLP]


  144. A Quantitative Prediction Model for Hardware/Software Partitioning. [Citation Graph (, )][DBLP]


  145. Caching in Real-time Reconfiguration Port Scheduling. [Citation Graph (, )][DBLP]


  146. Effective Automatic Memory Allocation Algorithm Based on Schedule Length in Cycles in a Novel C to FPGA Compiler. [Citation Graph (, )][DBLP]


  147. Wirelength Prediction for FPGAs. [Citation Graph (, )][DBLP]


  148. CuNoC: A Scalable Dynamic NoC for Dynamically Reconfigurable FPGAs. [Citation Graph (, )][DBLP]


  149. System-level Modelling and Analysis of Embedded Reconfigurable Cores for Wireless Systems. [Citation Graph (, )][DBLP]


  150. A resource optimized SoC Kit for FPGAs. [Citation Graph (, )][DBLP]


  151. A Banded Smith-Waterman FPGA Accelerator for Mercury BLASTP. [Citation Graph (, )][DBLP]


  152. Compression system for the phonocardiographic signal. [Citation Graph (, )][DBLP]


  153. RLS Lattice Algorithm with Order Probability Evaluation as an Accelerator for the Microblaze Processor. [Citation Graph (, )][DBLP]


  154. NoC Implementation in FPGA Using Torus Topology. [Citation Graph (, )][DBLP]


  155. Microarchitectural Enhancements for Configurable Multi-Threaded Soft Processors. [Citation Graph (, )][DBLP]


  156. FPGA based Sparse Matrix Vector Multiplication using Commodity DRAM Memory. [Citation Graph (, )][DBLP]


  157. A Novel Event Based Simulation Algorithm for Sequential Digital Circuit Simulation. [Citation Graph (, )][DBLP]


  158. Design Methodology and Trade-offs Analysis for Parameterized Dynamically Reconfigurable Processor Arrays. [Citation Graph (, )][DBLP]


  159. An fpga based open source network-on-chip architecture. [Citation Graph (, )][DBLP]


  160. FlowContext: Flexible Platform for Multigigabit Stateful Packet Processing. [Citation Graph (, )][DBLP]


  161. A Combining technique of rate law functions for a cost-effective reconfigurable biological simulator. [Citation Graph (, )][DBLP]

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