Conferences in DBLP
The Intel Geneseo Project. [Citation Graph (, )][DBLP ] System-Level Design for FPGAs. [Citation Graph (, )][DBLP ] Adventures with a Reconfigurable Research Platform. [Citation Graph (, )][DBLP ] Redefining the FPGA for the Next Generation. [Citation Graph (, )][DBLP ] Design Space Exploration of the European Option Benchmark Using HyperStreams. [Citation Graph (, )][DBLP ] Accelerating a Medical 3D Brain MRI Analysis Algorithm using a High-Performance Reconfigurable Computer. [Citation Graph (, )][DBLP ] Soft-Hard 3D FD-TD Solver for Non Destructive Evaluation. [Citation Graph (, )][DBLP ] Array Synthesis in SystemC Hardware Compilation. [Citation Graph (, )][DBLP ] Floating-Point Trigonometric Functions for FPGAs. [Citation Graph (, )][DBLP ] A Method for Fast Hardware Specialization at run-time. [Citation Graph (, )][DBLP ] A Many-core Implementation based on the Reconfigurable Mesh Model. [Citation Graph (, )][DBLP ] An FPGA Approach to Quantifying Coherence Traffic Efficiency on Multiprocessor Systems. [Citation Graph (, )][DBLP ] RAMP Blue: A Message-Passing Manycore System in FPGAs. [Citation Graph (, )][DBLP ] A Radio Astronomy Correlator Optimized for the XILINX VIRTEX-4 SX FPGA. [Citation Graph (, )][DBLP ] TANOR: A Tool for Accelerating N-Body Simulations on Reconfigurable Platforms. [Citation Graph (, )][DBLP ] Performance Modeling of 2D Cellular Automata on FPGA. [Citation Graph (, )][DBLP ] Bringing High-Performance Reconfigurable Computing to Exact Computations. [Citation Graph (, )][DBLP ] Applying Out-of-Core QR Decomposition Algorithms on FPGA-Based Systems. [Citation Graph (, )][DBLP ] Multi-processor System-level Synthesis for Multiple Applications on Platform FPGA. [Citation Graph (, )][DBLP ] Supporting High Level Language Semantics Within Hardware Resident Threads. [Citation Graph (, )][DBLP ] Formal Modeling of Process Migration. [Citation Graph (, )][DBLP ] Dynamic Cache Switching in Reconfigurable Embedded Systems. [Citation Graph (, )][DBLP ] Improving Timing-Driven FPGA Packing With Physical Information. [Citation Graph (, )][DBLP ] Clock-Aware Placement for FPGAs. [Citation Graph (, )][DBLP ] Fast On-line Task Placement and Scheduling on Reconfigurable Devices. [Citation Graph (, )][DBLP ] A Hardware Algorithm for the Minimum p-Quasi Clique Cover Problem. [Citation Graph (, )][DBLP ] High speed tablation system using an FPGA designed for distribution tables of frequent DNA subsequences. [Citation Graph (, )][DBLP ] Discrete Event Simulation of Molecular Dynamics with Configurable Logic. [Citation Graph (, )][DBLP ] Pre-route Interconnect Capacitance and Power Estimation in FPGAs. [Citation Graph (, )][DBLP ] Exploiting Hardware and Software Low Power Techniques for Energy Efficient Co-scheduling in Dynamically Reconfigurable Systems. [Citation Graph (, )][DBLP ] A Power Estimation Model for an FPGA-based Softcore Processor. [Citation Graph (, )][DBLP ] A Software Defined Radio Application Utilizing Modern FPGAs and NoC Interconnects. [Citation Graph (, )][DBLP ] Intellectual Property Protection of HDL IP Cores Through Automated Sognature Hosting. [Citation Graph (, )][DBLP ] Physical Unclonable Functions, FPGAs and Public-Key Crypto for IP Protection. [Citation Graph (, )][DBLP ] Domain-Specific Hybrid FPGA: Architecture and Floating Point Applications. [Citation Graph (, )][DBLP ] Embedded Programmable Logic Core Enhancements for System Bus Interfaces. [Citation Graph (, )][DBLP ] Improving Pipelined Soft Processors with Multithreading. [Citation Graph (, )][DBLP ] An area-efficient alternative to adaptive median filtering in FPGAs. [Citation Graph (, )][DBLP ] An Efficient Implementation of a 2D DWT on FPGA. [Citation Graph (, )][DBLP ] H.264/AVC In-Loop De-Blocking Filter Targeting a Dynamically Reconfigurable Instruction Cell Based Architecture. [Citation Graph (, )][DBLP ] On the feasibility of early routing capacitance estimation for FPGAs. [Citation Graph (, )][DBLP ] Power Reduction in Network Equipment through Adaptive Partial Reconfiguration. [Citation Graph (, )][DBLP ] Adaptive Thermoregulation for Applications on Reconfigurable Devices. [Citation Graph (, )][DBLP ] FPGA Implementation of a Data-Driven Stochastic Biochemical Simulator with the Next Reaction Method. [Citation Graph (, )][DBLP ] GENDIV - A Hardware Algorithm for Intron and Exon String Detection in DNA Chains. [Citation Graph (, )][DBLP ] A Unified Streaming Architecture for Real Time Face Detection and Gender Classification. [Citation Graph (, )][DBLP ] Disjoint Pattern Enumeration for Custom Instructions Identification. [Citation Graph (, )][DBLP ] Fast and Accurate Interval-Based Timing Estimator for Variability-Aware FPGA Physical Synthesis Tools. [Citation Graph (, )][DBLP ] An Execution Model for Hardware/Software Compilation and its System-Level Realization. [Citation Graph (, )][DBLP ] Module Graph Merging and Placement to Reduce Reconfiguration Overheads in Paged FPGA Devices. [Citation Graph (, )][DBLP ] Layered Approach to Instrinsic Evolvable Hardware Using Direct Bistream Manipulation of VIRTEX II Pro Devices. [Citation Graph (, )][DBLP ] A generalized and unified SPFD-based rewiring technique. [Citation Graph (, )][DBLP ] Improving External Memory Access for Avalon Systems on Programmable Chips.. [Citation Graph (, )][DBLP ] Time Predictable CPU and DMA Shared Memory Access. [Citation Graph (, )][DBLP ] Virtualization on the Tartan Reconfigurable Architecture. [Citation Graph (, )][DBLP ] A Design Methodology for Communication Infrastructures on Partially Reconfigurable FPGAs. [Citation Graph (, )][DBLP ] Efficient FPGA-based multipliers for F_3^97 and F_3^(6*97). [Citation Graph (, )][DBLP ] Efficient mapping of a Kalman filter into an FPGA using Taylor Expansion. [Citation Graph (, )][DBLP ] Implementation of a Virtual Internal Configuration Access Port (JCAP) for Enabling Partial Self-Reconfiguration on Xilinx Spartan III FPGAs. [Citation Graph (, )][DBLP ] L4: An FPGA-Based Accelerator for Detailed Maze Routing. [Citation Graph (, )][DBLP ] Improving Annealing Via Directed Moves. [Citation Graph (, )][DBLP ] artNoC - A Novel Multi-Functional Router Architecture for Organic Computing. [Citation Graph (, )][DBLP ] A Time-Triggered Network-on-Chip. [Citation Graph (, )][DBLP ] A Temporal Correlation Based Port Combination Methodology for Networks-on-chip on Reconfigurable Systems. [Citation Graph (, )][DBLP ] Router Design for Application Specific Networks-on-Chip on Reconfigurable Systems. [Citation Graph (, )][DBLP ] The ANDRES Project: Analysis and Design of Run-Time Reconfigurable, Heterogeneous Systems. [Citation Graph (, )][DBLP ] HARTES Toolchain Early Evaluation: Profiling, Compilation and HDL Generation. [Citation Graph (, )][DBLP ] MORPHEUS: Heterogeneous Reconfigurable Computing. [Citation Graph (, )][DBLP ] On-line Routing of Reconfigurable Functions for Future Self-Adaptive Systems - Investigations within the ÆTHER Project. [Citation Graph (, )][DBLP ] Equivalence Verification of FPGA and Structured ASIC Implementations. [Citation Graph (, )][DBLP ] Statistical Generic And Chip-Specific Skew Assignment for Improving Timing Yield of FPGAs. [Citation Graph (, )][DBLP ] Fault Models and Yield Analysis for QCA-based PLAs. [Citation Graph (, )][DBLP ] ReconOS: An RTOS supporting Hard- and Software Threads. [Citation Graph (, )][DBLP ] The Design of Multitasking Based Applications on Reconfigurable Instruction Cell Bsed Architectures. [Citation Graph (, )][DBLP ] Monte Carlo Logarithmic Number System for Model Predictive Control. [Citation Graph (, )][DBLP ] Dynamic Voltage Scaling in a FPGA-based System-on-Chip. [Citation Graph (, )][DBLP ] Multiplexer-based routing fabric for reconfigurable logic. [Citation Graph (, )][DBLP ] H.264 Decoder at HD Resolution on a Coarse Grain Dynamically Reconfigurable Architecture. [Citation Graph (, )][DBLP ] Implementation on FPGA of a LUT-based atan(Y/X) operator suitable for Synchronization Algorithms. [Citation Graph (, )][DBLP ] Efficient Priority-Queue Data Structure for Hardware Implementation. [Citation Graph (, )][DBLP ] Compact AES-based Architecture for Symmetric Encryption, Hash Function, and Random Number Generation. [Citation Graph (, )][DBLP ] Design of a hardware accelerator for fingerprint alignment. [Citation Graph (, )][DBLP ] An FPGA Implementation of Multiple Sequence Alignment Based on Carrillo-Lipman Method. [Citation Graph (, )][DBLP ] An FPGA Solver for Very Large SAT Problems. [Citation Graph (, )][DBLP ] A Multi Objective GA based Physical Placement Algorithm for Heterogeneous Dynamically Reconfigurable Arrays. [Citation Graph (, )][DBLP ] Aggressive Loop Pipelining for Reconfigurable Architectures. [Citation Graph (, )][DBLP ] Comrade - A Compiler for Adaptive Computing Systems Using a Novel Fast Speculation Technique. [Citation Graph (, )][DBLP ] Self-Healing Circuits for Space-Applications. [Citation Graph (, )][DBLP ] Automatic Software Hardware Co-Design for Reconfigurable Computing Systems. [Citation Graph (, )][DBLP ] VPH - A Tool for Exploring Hybrid FPGAs. [Citation Graph (, )][DBLP ] Hybridthreads Compiler: Generation of Application Specific Hardware Thread Cores from C. [Citation Graph (, )][DBLP ] Wires On Demand: Run-Time Communication Synthesis for Reconfigurable Computing. [Citation Graph (, )][DBLP ] A Behavioral Synthesis Approach for Distributed Memory FPGA Architectures. [Citation Graph (, )][DBLP ] Mapping A VLIWxSIMD Processor on an FPGA: Scalability and Performance. [Citation Graph (, )][DBLP ] An Automatic Compilation Framework for Configurable Architectures. [Citation Graph (, )][DBLP ] A high throughput area time efficient pseudo uniform random number generator based on the TT800 algorithm. [Citation Graph (, )][DBLP ] Dynamic Partial FPGA Reconfiguration in a Prototype Microprocessor System. [Citation Graph (, )][DBLP ] A Load/Store Unit for a Memcpy Hardware Accelerator. [Citation Graph (, )][DBLP ] Incremental Fault Emulation. [Citation Graph (, )][DBLP ] A novel motion estimation power reduction technique. [Citation Graph (, )][DBLP ] A Variable Grain Logic Cell Architecture for Reconfigurable Logic Cores. [Citation Graph (, )][DBLP ] A High Speed License Plate Recognition System on an FPGA. [Citation Graph (, )][DBLP ] REDEFINE: Architecture of a SoC Fabric for Runtime Composition of Computation Structures. [Citation Graph (, )][DBLP ] Implementation of a 2-D 8x8 IDCT on the Reconfigurable Montium Core. [Citation Graph (, )][DBLP ] A Reprogrammable and Scalable Multimedia Traffic Generator/Monitor on FPGA. [Citation Graph (, )][DBLP ] C++ based design flow for reconfigurable image processing systems. [Citation Graph (, )][DBLP ] A floating-point Extended Kalman Filter implementation for autonomous mobile robots. [Citation Graph (, )][DBLP ] Efficient External Memory Interface for Multi-processor Platforms Realized on FPGA Chips. [Citation Graph (, )][DBLP ] Hardware/Software Process Migration and RTL Simulation. [Citation Graph (, )][DBLP ] Implementation of a barotropic operator for ocean model simulation using a reconfigurable machine. [Citation Graph (, )][DBLP ] Evolutionary Search Applied to Reconfigurable Analogue Control. [Citation Graph (, )][DBLP ] Soft IP core implementation of recursive least squares filter using only multplicative and additive operators. [Citation Graph (, )][DBLP ] Characterizing Effective Memory Bandwidth of Designs with Concurrent High-Performance Computing Cores. [Citation Graph (, )][DBLP ] A Design Flow to Map Parallel Applications onto FPGAs. [Citation Graph (, )][DBLP ] A Hybrid Reconfigurable Cluster-on-Chip Architecture With Message Passing Interface For Image Processing Applications. [Citation Graph (, )][DBLP ] Novel Multi-Layer floorplanning for Heterogeneous FPGAs. [Citation Graph (, )][DBLP ] Automatic Accuracy-Guaranteed Bit-Width Optimization for Fixed and Floating-Point Systems. [Citation Graph (, )][DBLP ] Accelerating Microblaze Floating Point Operations. [Citation Graph (, )][DBLP ] Analysis of Kernel Effects on Optimisation Mismatch in Cache Reconfiguration. [Citation Graph (, )][DBLP ] High Level Power Optimization by Type Inference on the Generation of Application Specific Circuits on FPGAs. [Citation Graph (, )][DBLP ] Dynamically reconfigurable dataflow architecture for high-performance digital signal processing on multi-FPGA platforms. [Citation Graph (, )][DBLP ] RIC Fast Adder and its Set Tolerant Implementation in FPGAs. [Citation Graph (, )][DBLP ] Solving RC5 Challenges with Hardware -- a Distributed.net Perspective --. [Citation Graph (, )][DBLP ] High Level Abstraction Language as an Alternative to Embedded Processors for Internet Packet Processing in FPGA. [Citation Graph (, )][DBLP ] Exploring Alternative 3D FPGA Architectures: Design Methodology and CAD Tool Support. [Citation Graph (, )][DBLP ] AdaBoost Engine. [Citation Graph (, )][DBLP ] An FPGA Based Memory Efficient Shared Buffer Implementation. [Citation Graph (, )][DBLP ] Efficient Modeling and Floorplanning of Embedded-FPGA Fabric. [Citation Graph (, )][DBLP ] A New Scalable Hardware Architecture for RSA Algorithm. [Citation Graph (, )][DBLP ] Implementation of Low Frequency Finite State Machines Using the VIRTEX SRL16 Primitive. [Citation Graph (, )][DBLP ] Run-time Partial Reconfiguration for Removal, Placement and Routing on the Virtex-II-Pro. [Citation Graph (, )][DBLP ] Dynamic reconfiguration management based on a distributed object model. [Citation Graph (, )][DBLP ] Circuit Switched Run-Time Adaptive Network-on-Chip for Image Processing Applications. [Citation Graph (, )][DBLP ] An OCM based shared Memory controller for Virtex 4. [Citation Graph (, )][DBLP ] DWARV: DelftWorkBench Automated Reconfigurable VHDL Generator. [Citation Graph (, )][DBLP ] Accelerating tool path computing in CAD/CAM: A FPGA architecture for turning lathe machining.. [Citation Graph (, )][DBLP ] Exploiting Analog and Digital Reconfiguration for Smart Sensor Interfacing. [Citation Graph (, )][DBLP ] SoPC architecture for a Key Point Detector. [Citation Graph (, )][DBLP ] A Pipeline Implementation of a Watershed Algorithm on FPGA. [Citation Graph (, )][DBLP ] FPGA Implementation of 64-bit Exponential Function for HPC. [Citation Graph (, )][DBLP ] A Graphical Model-Level Debugger for Heterogenous Reconfigurable Architectures. [Citation Graph (, )][DBLP ] A Run-time Reconfigurable Processor for Video Motion Estimation. [Citation Graph (, )][DBLP ] Confiuartion Management in the Context of Self Adapative Systems. [Citation Graph (, )][DBLP ] A Quantitative Prediction Model for Hardware/Software Partitioning. [Citation Graph (, )][DBLP ] Caching in Real-time Reconfiguration Port Scheduling. [Citation Graph (, )][DBLP ] Effective Automatic Memory Allocation Algorithm Based on Schedule Length in Cycles in a Novel C to FPGA Compiler. [Citation Graph (, )][DBLP ] Wirelength Prediction for FPGAs. [Citation Graph (, )][DBLP ] CuNoC: A Scalable Dynamic NoC for Dynamically Reconfigurable FPGAs. [Citation Graph (, )][DBLP ] System-level Modelling and Analysis of Embedded Reconfigurable Cores for Wireless Systems. [Citation Graph (, )][DBLP ] A resource optimized SoC Kit for FPGAs. [Citation Graph (, )][DBLP ] A Banded Smith-Waterman FPGA Accelerator for Mercury BLASTP. [Citation Graph (, )][DBLP ] Compression system for the phonocardiographic signal. [Citation Graph (, )][DBLP ] RLS Lattice Algorithm with Order Probability Evaluation as an Accelerator for the Microblaze Processor. [Citation Graph (, )][DBLP ] NoC Implementation in FPGA Using Torus Topology. [Citation Graph (, )][DBLP ] Microarchitectural Enhancements for Configurable Multi-Threaded Soft Processors. [Citation Graph (, )][DBLP ] FPGA based Sparse Matrix Vector Multiplication using Commodity DRAM Memory. [Citation Graph (, )][DBLP ] A Novel Event Based Simulation Algorithm for Sequential Digital Circuit Simulation. [Citation Graph (, )][DBLP ] Design Methodology and Trade-offs Analysis for Parameterized Dynamically Reconfigurable Processor Arrays. [Citation Graph (, )][DBLP ] An fpga based open source network-on-chip architecture. [Citation Graph (, )][DBLP ] FlowContext: Flexible Platform for Multigigabit Stateful Packet Processing. [Citation Graph (, )][DBLP ] A Combining technique of rate law functions for a cost-effective reconfigurable biological simulator. [Citation Graph (, )][DBLP ]