Conferences in DBLP
Customizable domain-specific computing. [Citation Graph (, )][DBLP ] In search of agile hardware. [Citation Graph (, )][DBLP ] The evolution of architecture exploration of programmable devices. [Citation Graph (, )][DBLP ] FPGA challenges and opportunities at 40nm and beyond. [Citation Graph (, )][DBLP ] Virtex-6 and Spartan-6, plus a look into the future. [Citation Graph (, )][DBLP ] MuCCRA-Cube: A 3D dynamically reconfigurable processor with inductive-coupling link. [Citation Graph (, )][DBLP ] Hardware implementation of MPI_Barrier on an FPGA cluster. [Citation Graph (, )][DBLP ] Fast critical sections via thread scheduling for FPGA-based multithreaded processors. [Citation Graph (, )][DBLP ] A biophysically accurate floating point somatic neuroprocessor. [Citation Graph (, )][DBLP ] CNP: An FPGA-based processor for Convolutional Networks. [Citation Graph (, )][DBLP ] Noise impact of single-event upsets on an FPGA-based digital filter. [Citation Graph (, )][DBLP ] Compiler assisted runtime task scheduling on a reconfigurable computer. [Citation Graph (, )][DBLP ] Data parallel FPGA workloads: Software versus hardware. [Citation Graph (, )][DBLP ] Generating high-performance custom floating-point pipelines. [Citation Graph (, )][DBLP ] Performance comparison of single-precision SPICE Model-Evaluation on FPGA, GPU, Cell, and multi-core processors. [Citation Graph (, )][DBLP ] Exploring reconfigurable architectures for explicit finite difference option pricing models. [Citation Graph (, )][DBLP ] Towards a viable out-of-order soft core: Copy-Free, checkpointed register renaming. [Citation Graph (, )][DBLP ] A runtime relocation based workflow for self dynamic reconfigurable systems design. [Citation Graph (, )][DBLP ] An integrated tool flow to realize runtime-reconfigurable applications on a new class of partial multi-context FPGAs. [Citation Graph (, )][DBLP ] FPGA partial reconfiguration via configuration scrubbing. [Citation Graph (, )][DBLP ] Improving logic density through synthesis-inspired architecture. [Citation Graph (, )][DBLP ] Clock gating architectures for FPGA power reduction. [Citation Graph (, )][DBLP ] Program-driven fine-grained power management for the reconfigurable mesh. [Citation Graph (, )][DBLP ] Performance comparison of FPGA, GPU and CPU in image processing. [Citation Graph (, )][DBLP ] Self-organizing multi-cue fusion for FPGA-based embedded imaging. [Citation Graph (, )][DBLP ] Optimizing the SUSAN corner detection algorithm for a high speed FPGA implementation. [Citation Graph (, )][DBLP ] An analytical model relating FPGA architecture and place and route runtime. [Citation Graph (, )][DBLP ] Replace: An incremental placement algorithm for field programmable gate arrays. [Citation Graph (, )][DBLP ] Optimal runtime reconfiguration strategies for systolic arrays. [Citation Graph (, )][DBLP ] A multi-FPGA architecture for stochastic Restricted Boltzmann Machines. [Citation Graph (, )][DBLP ] Comparing fine-grained performance on the Ambric MPPA against an FPGA. [Citation Graph (, )][DBLP ] Low power techniques for Motion Estimation hardware. [Citation Graph (, )][DBLP ] Coarse-grained dynamically reconfigurable architecture with flexible reliability. [Citation Graph (, )][DBLP ] A novel SRAM-based FPGA architecture for efficient TMR fault tolerance support. [Citation Graph (, )][DBLP ] Reconfigurable fault tolerance: A framework for environmentally adaptive fault mitigation in space. [Citation Graph (, )][DBLP ] Modeling post-techmapping and post-clustering FPGA circuit depth. [Citation Graph (, )][DBLP ] Globally optimal time-multiplexing in inter-FPGA connections for accelerating multi-FPGA systems. [Citation Graph (, )][DBLP ] An ASIC perspective on FPGA optimizations. [Citation Graph (, )][DBLP ] Recursion in reconfigurable computing: A survey of implementation approaches. [Citation Graph (, )][DBLP ] A comparison of FPGA and FPAA technologies for a signal processing application. [Citation Graph (, )][DBLP ] A radix-8 complex divider for FPGA implementation. [Citation Graph (, )][DBLP ] Exploiting fast carry-chains of FPGAs for designing compressor trees. [Citation Graph (, )][DBLP ] Large multipliers with fewer DSP blocks. [Citation Graph (, )][DBLP ] Area estimation and optimisation of FPGA routing fabrics. [Citation Graph (, )][DBLP ] In field, energy-performance tunable FPGA architectures. [Citation Graph (, )][DBLP ] Static versus scheduled interconnect in Coarse-Grained Reconfigurable Arrays. [Citation Graph (, )][DBLP ] A fast parallel matrix multiplication reconfigurable unit utilized in face recognitions systems. [Citation Graph (, )][DBLP ] Design space exploration of reconfigurable systems for calculating flying object's optimal noise reduction paths. [Citation Graph (, )][DBLP ] Real-time processing of local contrast enhancement on FPGA. [Citation Graph (, )][DBLP ] Enhancements to FPGA design methodology using streaming. [Citation Graph (, )][DBLP ] General methodology for mapping iterative approximation algorithms to adaptive dynamically partially reconfigurable systems. [Citation Graph (, )][DBLP ] Optimising designs by combining model-based and pattern-based transformations. [Citation Graph (, )][DBLP ] sFPGA2 - A scalable GALS FPGA architecture and design methodology. [Citation Graph (, )][DBLP ] Star-Wheels Network-on-Chip featuring a self-adaptive mixed topology and a synergy of a circuit - and a packet-switching communication protocol. [Citation Graph (, )][DBLP ] A new deadlock-free fault-tolerant routing algorithm for NoC interconnections. [Citation Graph (, )][DBLP ] Accelerating HMMER search using FPGA. [Citation Graph (, )][DBLP ] An accelerator for K-TH nearest neighbor thinning based on the IMORC infrastructure. [Citation Graph (, )][DBLP ] Efficient particle-pair filtering for acceleration of molecular dynamics simulation. [Citation Graph (, )][DBLP ] Implementation of a reconfigurable Fast Fourier Transform application to digital terrestrial television broadcasting. [Citation Graph (, )][DBLP ] Design and evaluation of an energy-efficient dynamically reconfigurable architecture for wireless sensor nodes. [Citation Graph (, )][DBLP ] A highly scalable Restricted Boltzmann Machine FPGA implementation. [Citation Graph (, )][DBLP ] Pipeline implementation of the 128-bit block cipher CLEFIA in FPGA. [Citation Graph (, )][DBLP ] Clock duplicity for high-precision timestamping in Gigabit Ethernet. [Citation Graph (, )][DBLP ] DPA resistance for light-weight implementations of cryptographic algorithms on FPGAs. [Citation Graph (, )][DBLP ] Increasing stability and distinguishability of the digital fingerprint in FPGAs through input word analysis. [Citation Graph (, )][DBLP ] Towards a unique FPGA-based identification circuit using process variations. [Citation Graph (, )][DBLP ] IP protection in Partially Reconfigurable FPGAs. [Citation Graph (, )][DBLP ] FPGA accelerating three QR decomposition algorithms in the unified pipelined framework. [Citation Graph (, )][DBLP ] FPGA-accelerated Information Retrieval: High-efficiency document filtering. [Citation Graph (, )][DBLP ] A toolset for the analysis and optimization of motion estimation algorithms and processors. [Citation Graph (, )][DBLP ] Acceleration of complex algorithms on a fast reconfigurable embedded system on Spartan-3. [Citation Graph (, )][DBLP ] Building heterogeneous reconfigurable systems using threads. [Citation Graph (, )][DBLP ] Reconfiguration-based time-to-digital converter for Virtex FPGAs. [Citation Graph (, )][DBLP ] An efficient reconfigurable architecture to implement dense stereo vision algorithm using high-level synthesis. [Citation Graph (, )][DBLP ] High speed fixed point dividers for FPGAs. [Citation Graph (, )][DBLP ] A self-reconfiguring architecture supporting multiple objective functions in genetic algorithms. [Citation Graph (, )][DBLP ] Automatic generation of FPGA hardware accelerators using a domain specific language. [Citation Graph (, )][DBLP ] A dynamically reconfigurable parallel pixel processing system. [Citation Graph (, )][DBLP ] An approach to system-wide fault tolerance for FPGAs. [Citation Graph (, )][DBLP ] A multi-layered XML schema and design tool for reusing and integrating FPGA IP. [Citation Graph (, )][DBLP ] Bitstream compression through frame removal and partial reconfiguration. [Citation Graph (, )][DBLP ] Operation scheduling for FPGA-based reconfigurable computers. [Citation Graph (, )][DBLP ] FPGA-accelerated retinal vessel-tree extraction. [Citation Graph (, )][DBLP ] Novel strategies for hardware acceleration of frequent itemset mining with the apriori algorithm. [Citation Graph (, )][DBLP ] Dynamic Polymorphic Reconfiguration for anti-tamper circuits. [Citation Graph (, )][DBLP ] Run-time Partial Reconfiguration speed investigation and architectural design space exploration. [Citation Graph (, )][DBLP ] Dynamic reconfigurable mixed-signal architecture for safety critical applications. [Citation Graph (, )][DBLP ] Using 3D integration technology to realize multi-context FPGAs. [Citation Graph (, )][DBLP ] Mems optically reconfigurable gate array. [Citation Graph (, )][DBLP ] Sharf: An FPGA-based customizable processor architecture. [Citation Graph (, )][DBLP ] Multigigabit network traffic processing. [Citation Graph (, )][DBLP ] Macs: A Minimal Adaptive routing circuit-switched architecture for scalable and parametric NoCs. [Citation Graph (, )][DBLP ] Fine Grain Partial Reconfiguration for energy saving in Dynamically Reconfigurable Processors. [Citation Graph (, )][DBLP ] A low cost reconfigurable soft processor for multimedia applications: Design synthesis and programming model. [Citation Graph (, )][DBLP ] Rapid design exploration framework for application-aware customization of soft core processors. [Citation Graph (, )][DBLP ] A novel states recovery technique for the TMR softcore processor. [Citation Graph (, )][DBLP ] Performance metrics for hybrid multi-tasking systems. [Citation Graph (, )][DBLP ] Cooperative multithreading in dynamically reconfigurable systems. [Citation Graph (, )][DBLP ] The educational processor Sweet-16. [Citation Graph (, )][DBLP ] Secure FPGA technologies and techniques. [Citation Graph (, )][DBLP ] FPGA supercomputing platforms: A survey. [Citation Graph (, )][DBLP ] A novel SEU, MBU and SHE handling strategy for Xilinx Virtex-4 FPGAs. [Citation Graph (, )][DBLP ] Run-time resource management in fault-tolerant network on reconfigurable chips. [Citation Graph (, )][DBLP ] Hot-Swapping architecture extension for mitigation of permanent functional unit faults. [Citation Graph (, )][DBLP ] SVM speaker verification system based on a low-cost FPGA. [Citation Graph (, )][DBLP ] An FPGA-based embedded wideband audio codec system. [Citation Graph (, )][DBLP ] Off-line placement of hardware tasks on FPGA. [Citation Graph (, )][DBLP ] Proteus: An architectural synthesis tool based on the stream programming paradigm. [Citation Graph (, )][DBLP ] Binary Synthesis with multiple memory banks targeting array references. [Citation Graph (, )][DBLP ] Mapping basic prefix computations to fast carry-chain structures. [Citation Graph (, )][DBLP ] FPGA-implementation of Time-Multiplexed Multiple Constant Multiplication based on carry-save arithmetic. [Citation Graph (, )][DBLP ] Compensating for variability in FPGAs by re-mapping and re-placement. [Citation Graph (, )][DBLP ] Synthesis of the SR programming language for complex FPGAs. [Citation Graph (, )][DBLP ] Exploiting synchronous placement for asynchronous circuits onto commercial FPGAs. [Citation Graph (, )][DBLP ] Using C-to-gates to program streaming image processing kernels efficiently on FPGAs. [Citation Graph (, )][DBLP ] An FPGA based verification platform for HyperTransport 3.x. [Citation Graph (, )][DBLP ] A virus scanning engine using a parallel finite-input memory machine and MPUs. [Citation Graph (, )][DBLP ] Tracking elephant flows in internet backbone traffic with an FPGA-based cache. [Citation Graph (, )][DBLP ] A reconfigurable FIR/FFT unit for wireless telecommunication systems. [Citation Graph (, )][DBLP ] Efficient AES S-boxes implementation for non-volatile FPGAs. [Citation Graph (, )][DBLP ] Modularizing flux limiter functions for a Computational Fluid Dynamics accelerator on FPGAs. [Citation Graph (, )][DBLP ] Compact FPGA implementation of Camellia. [Citation Graph (, )][DBLP ] FPGA-based acceleration of neural network for ranking in web search engine with a streaming architecture. [Citation Graph (, )][DBLP ] An FPGA design for evaluating score function in protein energy calculation. [Citation Graph (, )][DBLP ] Emulating Spiking Neural Networks for edge detection on FPGA hardware. [Citation Graph (, )][DBLP ] A reconfigurable architecture for the Phylogenetic Likelihood Function. [Citation Graph (, )][DBLP ] Configuring area and performance: Empirical evaluation on an FPGA-based biochemical simulator. [Citation Graph (, )][DBLP ] A FPGA based coprocessor for gene finding using Interpolated Markov Model (IMM). [Citation Graph (, )][DBLP ] Enhanced gradient-based motion vector coprocessor. [Citation Graph (, )][DBLP ] Dynamic reconfiguration system for real-time video processing. [Citation Graph (, )][DBLP ] Numerically controlled oscillators using linear approximation. [Citation Graph (, )][DBLP ] Random numbers generation: Investigation of narrowtransitions suppression on FPGA. [Citation Graph (, )][DBLP ] Improving the quality of a Physical Unclonable Function using configurable Ring Oscillators. [Citation Graph (, )][DBLP ] CREMA: A coarse-grain reconfigurable array with mapping adaptiveness. [Citation Graph (, )][DBLP ] High-level programming of coarse-grained reconfigurable architectures. [Citation Graph (, )][DBLP ] FPGA support for satellite computations of hyper spectral images. [Citation Graph (, )][DBLP ] Improving the memory footprint and runtime scalability of FPGA CAD algorithms. [Citation Graph (, )][DBLP ] Efficient techniques and methodologies for embedded system design usign free hardware and open standards. [Citation Graph (, )][DBLP ] Multi-terminal BDD synthesis and applications. [Citation Graph (, )][DBLP ] Soft errors in Flash-based FPGAs: Analysis methodologies and first results. [Citation Graph (, )][DBLP ] RISPP: A run-time adaptive reconfigurable embedded processor. [Citation Graph (, )][DBLP ] 