Conferences in DBLP

ACM Great Lakes Symposium on VLSI (glvlsi)
2010 (conf/glvlsi/2010)

1. 
   A novel design framework for the design of reconfigurable systems based on NoCs. [Citation Graph (, )][DBLP]
   
   
2. 
   A new physical routing approach for robust bundled signaling on NoC links. [Citation Graph (, )][DBLP]
   
   
3. 
   Bus via reduction based on floorplan revising. [Citation Graph (, )][DBLP]
   
   
4. 
   Timing-driven variation-aware nonuniform clock mesh synthesis. [Citation Graph (, )][DBLP]
   
   
5. 
   Scaling power/ground solvers on multi-core with memory bandwidth awareness. [Citation Graph (, )][DBLP]
   
   
6. 
   Bus-pin-aware bus-driven floorplanning. [Citation Graph (, )][DBLP]
   
   
7. 
   8Gb/s capacitive low power and high speed 4-PWAM transceiver design. [Citation Graph (, )][DBLP]
   
   
8. 
   A low power, variable resolution two-step flash ADC. [Citation Graph (, )][DBLP]
   
   
9. 
   A low-offset high-speed double-tail dual-rail dynamic latched comparator. [Citation Graph (, )][DBLP]
   
   
10. 
    Via configurable three-input lookup-tables for structured ASICs. [Citation Graph (, )][DBLP]
    
    
11. 
    Variation tolerant 9T SRAM cell design. [Citation Graph (, )][DBLP]
    
    
12. 
    Stochastic computational models for accurate reliability evaluation of logic circuits. [Citation Graph (, )][DBLP]
    
    
13. 
    A multi-level approach to reduce the impact of NBTI on processor functional units. [Citation Graph (, )][DBLP]
    
    
14. 
    Graph theoretic approach for scan cell reordering to minimize peak shift power. [Citation Graph (, )][DBLP]
    
    
15. 
    Gating internal nodes to reduce power during scan shift. [Citation Graph (, )][DBLP]
    
    
16. 
    Software adaptation in quality sensitive applications to deal with hardware variability. [Citation Graph (, )][DBLP]
    
    
17. 
    Write activity reduction on flash main memory via smart victim cache. [Citation Graph (, )][DBLP]
    
    
18. 
    Aging effects of leakage optimizations for caches. [Citation Graph (, )][DBLP]
    
    
19. 
    Thermal-aware floorplanning exploration for 3D multi-core architectures. [Citation Graph (, )][DBLP]
    
    
20. 
    A mask double patterning technique using litho simulation by wavelet transform. [Citation Graph (, )][DBLP]
    
    
21. 
    An effective approach for large scale floorplanning. [Citation Graph (, )][DBLP]
    
    
22. 
    A novel resource sharing model and high-level synthesis for delay variability-tolerant datapaths. [Citation Graph (, )][DBLP]
    
    
23. 
    A revisit to voltage partitioning problem. [Citation Graph (, )][DBLP]
    
    
24. 
    Resource-constrained timing-driven link insertion for critical delay reduction. [Citation Graph (, )][DBLP]
    
    
25. 
    Boolean satisfiability on a graphics processor. [Citation Graph (, )][DBLP]
    
    
26. 
    Pattern grading for testing critical paths considering power supply noise and crosstalk using a layout-aware quality metric. [Citation Graph (, )][DBLP]
    
    
27. 
    Improving the testability and reliability of sequential circuits with invariant logic. [Citation Graph (, )][DBLP]
    
    
28. 
    Deterministic broadside test generation for transition path delay faults. [Citation Graph (, )][DBLP]
    
    
29. 
    A delay measurement method using a shrinking clock signal. [Citation Graph (, )][DBLP]
    
    
30. 
    Energy-efficient redundant execution for chip multiprocessors. [Citation Graph (, )][DBLP]
    
    
31. 
    On-die sensors for measuring process and environmental variations in integrated circuits. [Citation Graph (, )][DBLP]
    
    
32. 
    Cost aware fault tolerant logic synthesis in presence of soft errors. [Citation Graph (, )][DBLP]
    
    
33. 
    Design of embedded MRAM macros for memory-in-logic applications. [Citation Graph (, )][DBLP]
    
    
34. 
    Topology impact on the room temperature performance of THz-range ballistic deflection transistors. [Citation Graph (, )][DBLP]
    
    
35. 
    Performance assessment of analog circuits with carbon nanotube FET (CNFET). [Citation Graph (, )][DBLP]
    
    
36. 
    Read-out schemes for a CNTFET-based crossbar memory. [Citation Graph (, )][DBLP]
    
    
37. 
    Synthetic biology: from modules to systems. [Citation Graph (, )][DBLP]
    
    
38. 
    Dominant critical gate identification for power and yield optimization in logic circuits. [Citation Graph (, )][DBLP]
    
    
39. 
    Logic synthesis for low power using clock gating and rewiring. [Citation Graph (, )][DBLP]
    
    
40. 
    Dynamically resizable binary decision diagrams. [Citation Graph (, )][DBLP]
    
    
41. 
    Fast instruction cache modeling for approximate timed HW/SW co-simulation. [Citation Graph (, )][DBLP]
    
    
42. 
    Clock skew reduction by self-compensating manufacturing variability with on-chip sensors. [Citation Graph (, )][DBLP]
    
    
43. 
    Online convex optimization-based algorithm for thermal management of MPSoCs. [Citation Graph (, )][DBLP]
    
    
44. 
    Overscaling-friendly timing speculation architectures. [Citation Graph (, )][DBLP]
    
    
45. 
    A model to exploit power-performance efficiency in superscalar processors via structure resizing. [Citation Graph (, )][DBLP]
    
    
46. 
    Thermal-aware compilation for system-on-chip processing architectures. [Citation Graph (, )][DBLP]
    
    
47. 
    A linear statistical analysis for full-chip leakage power with spatial correlation. [Citation Graph (, )][DBLP]
    
    
48. 
    Semi-analytical model for schottky-barrier carbon nanotube and graphene nanoribbon transistors. [Citation Graph (, )][DBLP]
    
    
49. 
    Lightweight runtime control flow analysis for adaptive loop caching. [Citation Graph (, )][DBLP]
    
    
50. 
    Low power nanoscale buffer management for network on chip routers. [Citation Graph (, )][DBLP]
    
    
51. 
    TURBONFS: turbo nand flash search. [Citation Graph (, )][DBLP]
    
    
52. 
    Write buffer-oriented energy reduction in the L1 data cache of two-level caches for the embedded system. [Citation Graph (, )][DBLP]
    
    
53. 
    Graphene tunneling FET and its applications in low-power circuit design. [Citation Graph (, )][DBLP]
    
    
54. 
    Scalable identification of threshold logic functions. [Citation Graph (, )][DBLP]
    
    
55. 
    Manufacturing yield of QCA circuits by synthesized DNA self-assembled templates. [Citation Graph (, )][DBLP]
    
    
56. 
    Numerical queue solution of thermal noise-induced soft errors in subthreshold CMOS devices. [Citation Graph (, )][DBLP]
    
    
57. 
    Design considerations for variation tolerant multilevel CMOS/Nano memristor memory. [Citation Graph (, )][DBLP]
    
    
58. 
    An integrated thermal estimation framework for industrial embedded platforms. [Citation Graph (, )][DBLP]
    
    
59. 
    Power-efficient, reliable microprocessor architectures: modeling and design methods. [Citation Graph (, )][DBLP]
    
    
60. 
    Performance and energy trade-offs analysis of L2 on-chip cache architectures for embedded MPSoCs. [Citation Graph (, )][DBLP]
    
    
61. 
    A virtual platform environment for exploring power, thermal and reliability management control strategies in high-performance multicores. [Citation Graph (, )][DBLP]
    
    
62. 
    Challenges and methodologies for efficient power budgeting across the die. [Citation Graph (, )][DBLP]
    
    
63. 
    A DOE-ILP assisted conjugate-gradient based power and stability optimization in High-K Nano-CMOS SRAM. [Citation Graph (, )][DBLP]
    
    
64. 
    Line width optimization for interdigitated power/ground networks. [Citation Graph (, )][DBLP]
    
    
65. 
    Thermal-aware voltage droop compensation for multi-core architectures. [Citation Graph (, )][DBLP]
    
    
66. 
    Analysis and mitigation of NBTI-impact on PVT variability in repeated global interconnect performance. [Citation Graph (, )][DBLP]
    
    
67. 
    Collaborative voltage scaling with online STA and variable-latency datapath. [Citation Graph (, )][DBLP]
    
    
68. 
    AOP-based high-level power estimation in SystemC. [Citation Graph (, )][DBLP]
    
    
69. 
    A novel crosstalk quantitative approach for simultaneously reducing power, noise, and delay based on bus-invert encoding schemes. [Citation Graph (, )][DBLP]
    
    
70. 
    The challenges of implementing fine-grained power gating. [Citation Graph (, )][DBLP]
    
    
71. 
    Performance and energy efficient cache migrationapproach for thermal management in embedded systems. [Citation Graph (, )][DBLP]
    
    
72. 
    Performance enhancement of subthreshold circuits using substrate biasing and charge-boosting buffers. [Citation Graph (, )][DBLP]
    
    
73. 
    Reliability analysis of power gated SRAM under combined effects of NBTI and PBTI in nano-scale CMOS. [Citation Graph (, )][DBLP]
    
    
74. 
    On-chip point-of-load voltage regulator for distributed power supplies. [Citation Graph (, )][DBLP]
    
    
75. 
    VLSI implementation of a non-linear feedback shift register for high-speed cryptography applications. [Citation Graph (, )][DBLP]
    
    
76. 
    Out-of-order issue logic using sorting networks. [Citation Graph (, )][DBLP]
    
    
77. 
    On-chip power supply noise and its implications on timing. [Citation Graph (, )][DBLP]
    
    
78. 
    Characteristics of MS-CMOS logic in sub-32nm technologies. [Citation Graph (, )][DBLP]
    
    
79. 
    A self-adaptive scheduler for asymmetric multi-cores. [Citation Graph (, )][DBLP]
    
    
80. 
    Context-aware TLB preloading for interference reduction in embedded multi-tasked systems. [Citation Graph (, )][DBLP]
    
    
81. 
    Design of self correcting radiation hardened digital circuits using decoupled ground bus. [Citation Graph (, )][DBLP]
    
    
82. 
    A novel multi-objective instruction synthesis flow for application-specific instruction set processors. [Citation Graph (, )][DBLP]
    
    
83. 
    Electromagnetic interaction of on-chip antennas and CMOS metal layers for wireless IC interconnects. [Citation Graph (, )][DBLP]
    
    
84. 
    Ordered escape routing via routability-driven pin assignment. [Citation Graph (, )][DBLP]
    
    
85. 
    Temperature-constrained fixed-outline floorplanning for die-stacking system-in-package design. [Citation Graph (, )][DBLP]
    
    
86. 
    Performance-constrained template-driven retargeting for analog and RF layouts. [Citation Graph (, )][DBLP]
    
    
87. 
    Wirelength-driven force-directed 3D FPGA placement. [Citation Graph (, )][DBLP]
    
    
88. 
    A novel droplet routing algorithm for digital microfluidic biochips. [Citation Graph (, )][DBLP]
    
    
89. 
    Methodology to achieve higher tolerance to delay variations in synchronous circuits. [Citation Graph (, )][DBLP]
    
    
90. 
    Circuit-level NBTI macro-models for collaborative reliability monitoring. [Citation Graph (, )][DBLP]
    
    
91. 
    Low-power side-channel attack-resistant asynchronous S-box design for AES cryptosystems. [Citation Graph (, )][DBLP]
    
    
92. 
    Enhancing debugging of multiple missing control errors in reversible logic. [Citation Graph (, )][DBLP]
    
    
93. 
    Algorithm and hardware complexity reduction techniques for k-best sphere decoders. [Citation Graph (, )][DBLP]