Conferences in DBLP
Embedded Systems as Datacenters. [Citation Graph (, )][DBLP ] Larrabee: A Many-Core Intel Architecture for Visual Computing. [Citation Graph (, )][DBLP ] Remote Store Programming. [Citation Graph (, )][DBLP ] Low-Overhead, High-Speed Multi-core Barrier Synchronization. [Citation Graph (, )][DBLP ] Improving Performance by Reducing Aborts in Hardware Transactional Memory. [Citation Graph (, )][DBLP ] Energy and Throughput Efficient Transactional Memory for Embedded Multicore Systems. [Citation Graph (, )][DBLP ] Split Register Allocation: Linear Complexity Without the Performance Penalty. [Citation Graph (, )][DBLP ] Trace-Based Data Layout Optimizations for Multi-core Processors. [Citation Graph (, )][DBLP ] Buffer Sizing for Self-timed Stream Programs on Heterogeneous Distributed Memory Multiprocessors. [Citation Graph (, )][DBLP ] Automatically Tuning Sparse Matrix-Vector Multiplication for GPU Architectures. [Citation Graph (, )][DBLP ] Virtual Ways: Efficient Coherence for Architecturally Visible Storage in Automatic Instruction Set Extensions. [Citation Graph (, )][DBLP ] Accelerating XML Query Matching through Custom Stack Generation on FPGAs. [Citation Graph (, )][DBLP ] An Application-Aware Load Balancing Strategy for Network Processors. [Citation Graph (, )][DBLP ] Memory-Aware Application Mapping on Coarse-Grained Reconfigurable Arrays. [Citation Graph (, )][DBLP ] Maestro: Orchestrating Lifetime Reliability in Chip Multiprocessors. [Citation Graph (, )][DBLP ] Combining Locality Analysis with Online Proactive Job Co-scheduling in Chip Multiprocessors. [Citation Graph (, )][DBLP ] RELOCATE: Register File Local Access Pattern Redistribution Mechanism for Power and Thermal Management in Out-of-Order Embedded Processor. [Citation Graph (, )][DBLP ] Performance and Power Aware CMP Thread Allocation Modeling. [Citation Graph (, )][DBLP ] Multi-level Hardware Prefetching Using Low Complexity Delta Correlating Prediction Tables with Partial Matching. [Citation Graph (, )][DBLP ] Scalable Shared-Cache Management by Containing Thrashing Workloads. [Citation Graph (, )][DBLP ] SRP: Symbiotic Resource Partitioning of the Memory Hierarchy in CMPs. [Citation Graph (, )][DBLP ] DIEF: An Accurate Interference Feedback Mechanism for Chip Multiprocessor Memory Systems. [Citation Graph (, )][DBLP ] Tagged Procedure Calls (TPC ): Efficient Runtime Support for Task-Based Parallelism on the Cell Processor.Citation Graph (, )][DBLP ] Analysis of Task Offloading for Accelerators. [Citation Graph (, )][DBLP ] Offload - Automating Code Migration to Heterogeneous Multicore Systems. [Citation Graph (, )][DBLP ] Computer Generation of Efficient Software Viterbi Decoders. [Citation Graph (, )][DBLP ] 