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Conferences in DBLP
Intel's Tera-scale Computing Project: The first five years, the next five years. [Citation Graph (, )][DBLP]
Design and implementation of the blue gene/P snoop filter. [Citation Graph (, )][DBLP]
Fabric convergence implications on systems architecture. [Citation Graph (, )][DBLP]
Prediction of CPU idle-busy activity pattern. [Citation Graph (, )][DBLP]
Performance-aware speculation control using wrong path usefulness prediction. [Citation Graph (, )][DBLP]
PaCo: Probability-based path confidence prediction. [Citation Graph (, )][DBLP]
Branch-mispredict level parallelism (BLP) for control independence. [Citation Graph (, )][DBLP]
Address-branch correlation: A novel locality for long-latency hard-to-predict branches. [Citation Graph (, )][DBLP]
EXCES: External caching in energy saving storage systems. [Citation Graph (, )][DBLP]
Cluster-level feedback power control for performance optimization. [Citation Graph (, )][DBLP]
C-Oracle: Predictive thermal management for data centers. [Citation Graph (, )][DBLP]
System level analysis of fast, per-core DVFS using on-chip switching regulators. [Citation Graph (, )][DBLP]
PEEP: Exploiting predictability of memory dependences in SMT processors. [Citation Graph (, )][DBLP]
Runahead Threads to improve SMT performance. [Citation Graph (, )][DBLP]
Single-level integrity and confidentiality protection for distributed shared memory multiprocessors. [Citation Graph (, )][DBLP]
FlexiTaint: A programmable accelerator for dynamic taint propagation. [Citation Graph (, )][DBLP]
Amdahl's Law in the multicore era. [Citation Graph (, )][DBLP]
CMP network-on-chip overlaid with multi-band RF-interconnect. [Citation Graph (, )][DBLP]
Regional congestion awareness for load balance in networks-on-chip. [Citation Graph (, )][DBLP]
Performance and power optimization through data compression in Network-on-Chip architectures. [Citation Graph (, )][DBLP]
Automated microprocessor stressmark generation. [Citation Graph (, )][DBLP]
Roughness of microarchitectural design topologies and its implications for optimization. [Citation Graph (, )][DBLP]
Fundamental performance constraints in horizontal fusion of in-order cores. [Citation Graph (, )][DBLP]
Serializing instructions in system-intensive workloads: Amdahl's Law strikes again. [Citation Graph (, )][DBLP]
Thread-safe dynamic binary translation using transactional memory. [Citation Graph (, )][DBLP]
Uncovering hidden loop level parallelism in sequential applications. [Citation Graph (, )][DBLP]
A comprehensive approach to DRAM power management. [Citation Graph (, )][DBLP]
Power-Efficient DRAM Speculation. [Citation Graph (, )][DBLP]
High-throughput pairwise point interactions in Anton, a specialized machine for molecular dynamics simulation. [Citation Graph (, )][DBLP]
Incorporating flexibility in Anton, a specialized machine for molecular dynamics simulation. [Citation Graph (, )][DBLP]
An OS-based alternative to full hardware coherence on tiled CMPs. [Citation Graph (, )][DBLP]
Gaining insights into multicore cache partitioning: Bridging the gap between simulation and real systems. [Citation Graph (, )][DBLP]
DeCoR: A Delayed Commit and Rollback mechanism for handling inductive noise in processors. [Citation Graph (, )][DBLP]
Supporting highly-decoupled thread-level redundancy for parallel programs. [Citation Graph (, )][DBLP]
Speculative instruction validation for performance-reliability trade-off. [Citation Graph (, )][DBLP]
Runtime validation of memory ordering using constraint graph checking. [Citation Graph (, )][DBLP]
Compilers and parallel computing systems. [Citation Graph (, )][DBLP]
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