Conferences in DBLP
Author Index. [Citation Graph (0, 0)][DBLP ] Conf ] Message from the Chairpersons. [Citation Graph (0, 0)][DBLP ] Conf ] Conference Organizers. [Citation Graph (0, 0)][DBLP ] Conf ] Referees. [Citation Graph (0, 0)][DBLP ] Conf ] A. Chihoub , Y. J. Bai , Visvanathan Ramesh An Imaging Library for a TriCore Based Digital Camera. [Citation Graph (0, 0)][DBLP ] Conf ] Frank Amiot , Edwige Pissaloux FreeTIV Parallel Computer: Architecture and Environment. [Citation Graph (0, 0)][DBLP ] Conf ] Dietrich Paulus , Christopher Drexler , Michael Reinhold , Matthias Zobel , Joachim Denzler Active Computer Vision System. [Citation Graph (0, 0)][DBLP ] Conf ] Gooitzen S. van der Wal , Michael W. Hansen , Michael R. Piacentino The Acadia Vision Processor. [Citation Graph (0, 0)][DBLP ] Conf ] Idaku Ishii , Takashi Komuro , Masatoshi Ishikawa Method of Moment Calculation for a Digital Vision Chip System. [Citation Graph (0, 0)][DBLP ] Conf ] Takashi Komuro , Idaku Ishii , Masatoshi Ishikawa , Atsushi Yoshida High Speed Target Tracking Vision Chip. [Citation Graph (0, 0)][DBLP ] Conf ] Jinsang Kim , Tom Chen A VLSI Architecture for Image Sequence Segmentation using Edge Fusion. [Citation Graph (0, 0)][DBLP ] Conf ] Pieter Jonker , Jie Han On Quantum and Classical Computing with Arrays of Superconducting Persistent Current Qubits. [Citation Graph (0, 0)][DBLP ] Conf ] Virginio Cantoni , Alfredo Petrosino 2-D Object Recognition by Structured Neural Networks in a Pyramidal Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Bimal Gisutham , Thambipillai Srikanthan , K. Vijayan Asari A High Speed Flat CORDIC Based Neuron with Multi-Level Activation Function for Robust Pattern Recognition. [Citation Graph (0, 0)][DBLP ] Conf ] Didier Dulac , Gilles Bertrand , Saloua Guezguez Parallel Segmentation Based on Topology with the Associative Net Model. [Citation Graph (0, 0)][DBLP ] Conf ] George A. Rovithakis , M. Maniadakis , Michalis Zervakis A Genetically Optimized Artificial Neural Network Structure for Feature Extraction and Classification of Vascular Tissue Fluorescence Spectrums. [Citation Graph (0, 0)][DBLP ] Conf ] Cesar Torres-Huitzil , Miguel Arias-Estrada An FPGA Architecture for High Speed Edge and Corner Detection. [Citation Graph (0, 0)][DBLP ] Conf ] Silvio P. Sabatini , P. Cavalleri , Fabio Solari , Giacomo M. Bisio Recovering 3-D Egomotion Parameters from Optic Flow: From Structural Principles to Analog Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Fernando Pardo , I. Llorens , F. Mico , Jose Antonio Boluda Space Variant Vision and Pipelined Architecture for Time to Impact Computation. [Citation Graph (0, 0)][DBLP ] Conf ] S. Bouaziz , M. Fan , Roger Reynaud , T. Maurin Multi-Sensors and Environment Simulator for Collision Avoidance Applications. [Citation Graph (0, 0)][DBLP ] Conf ] F. Verdier , Alain Mérigot , Bertrand Zavidovique Fast Stable Matching Algorithm using Asynchronous Parallel Programming Model. [Citation Graph (0, 0)][DBLP ] Conf ] Maria Grazia Albanesi , Alessandro Giancane Fast Retrieval on Compressed Images for Internet Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Wael M. Badawy , Magdy Bayoumi A Scalable Affine Core for Video Object Motion Compensation. [Citation Graph (0, 0)][DBLP ] Conf ] Roberto A. Reyna , Daniel Esteve , Dominique Houzet , Marie-France Albenge Implementation of the SVM Neural Network Generalization Function for Image Processing. [Citation Graph (0, 0)][DBLP ] Conf ] M. Aberbour , Habib Mehrez , François Durbin , Jacques Haussy , P. Lalande , André Tissot A System-On-A-Chip for Pattern Recognition Architecture and Design Methodology. [Citation Graph (0, 0)][DBLP ] Conf ] G. Coldani , L. Cotrino , Giovanni Danese , Francesco Leporati , M. Maneri Notacheck: A Parallel DSP-Based Architecture for Real Time High Resolution Inspection of Bank-Notes. [Citation Graph (0, 0)][DBLP ] Conf ] Nuno Roma , Leonel Sousa In the Development and Evaluation of Specialized Processors for Computing High-Order 2-D Image Moments in Real-Time. [Citation Graph (0, 0)][DBLP ] Conf ] Eugene Borovikov , Larry S. Davis A Distributed System for Real-Time Volume Reconstruction. [Citation Graph (0, 0)][DBLP ] Conf ] Vito Di Gesù , B. Lenzitti , Giosuè Lo Bosco , Domenico Tegolo A Distributed Architecture for Autonomous Navigation of Robots. [Citation Graph (0, 0)][DBLP ] Conf ] José Luis Bosque , Oscar David Robles , Angel Rodríguez , Luis Pastor Study of a Parallel CBIR Implementation using MPI. [Citation Graph (0, 0)][DBLP ] Conf ] Daisaku Arita , Satoshi Yonemoto , Rin-ichiro Taniguchi Real-Time Computer Vision on PC-Cluster and Its Application to Real-Time Motion Capture. [Citation Graph (0, 0)][DBLP ] Conf ] Nalini K. Ratha , Anil K. Jain , Diane T. Rover FPGA-Based Coprocessor for Text String Extraction. [Citation Graph (0, 0)][DBLP ] Conf ] Bruce A. Draper , Walid A. Najjar , A. P. Wim Böhm , Jeffrey Hammes , Robert Rinker , Charlie Ross , Monica Chawathe , José Bins Compiling and Optimizing Image Processing Algorithms for FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Sebastien Vagnier , Hassane Essafi , Alain Mérigot A Configurable Processor Network for Document Management. [Citation Graph (0, 0)][DBLP ] Conf ] Didier Demigny , Lounis Kessal , R. Bourguiba , N. Boudouani How to Use High Speed Reconfigurable FPGA for Real Time Image Processing? [Citation Graph (0, 0)][DBLP ] Conf ] Marco Ferretti Multi-Media Extensions in Super-Pipelined Micro-Architectures. A New Case for SIMD Processing? [Citation Graph (0, 0)][DBLP ] Conf ] Nicola Zingirian , Massimo Maresca Loop Regularization for Image and Video Processing on Instruction Level Parallel Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Eric Senn , Bertrand Zavidovique Examples of Image Processing to Benefit from an Asynchronous Implementation. [Citation Graph (0, 0)][DBLP ] Conf ] Bertrand Ducourthial , Alain Mérigot , Nicolas Sicard Anet: A Programming Environment for Parallel Image Analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Martin C. Herbordt , Jade Cravy , Honghai Zhang , Calvin Lin , Hong Rao An Array Control Unit for High Performance SIMD Arrays. [Citation Graph (0, 0)][DBLP ] Conf ] Gianni Conte , Stefano Tommesani , Francesco Zanichelli The Long And Winding Road to High-Performance Image Processing with MMX/SSE. [Citation Graph (0, 0)][DBLP ] Conf ] Rita Cucchiara , Massimo Piccardi , Andrea Prati Hardware Prefetching Techniques for Cache Memories in Multimedia Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Andrzej Sluzek Hardware Supported Technique for Detecting Multi-Corners In Digital Contours. [Citation Graph (0, 0)][DBLP ] Conf ] Toshikazu Wada , Xiaojun Wu , Shogo Tokai , Takashi Matsuyama Homography Based Parallel Volume Intersection: Toward Real-Time Volume Reconstruction using Active Cameras. [Citation Graph (0, 0)][DBLP ] Conf ] Luigi Cinque , Stefano Levialdi , Luca Lombardi , Steven L. Tanimoto Handling Artifacts in Digitally Reproduced Documents. [Citation Graph (0, 0)][DBLP ] Conf ] Beth Wilson , Magdy A. Bayoumi Compressed-Domain Classification of Texture Images. [Citation Graph (0, 0)][DBLP ] Conf ] Luigi di Stefano , Stefano Mattoccia Fast Stereo Matching for the VIDET System using a General Purpose Processor with Multimedia Extensions. [Citation Graph (0, 0)][DBLP ] Conf ] 