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Conferences in DBLP

International Conference on Computer Aided Design (ICCAD) (iccad)
2007 (conf/iccad/2007)


  1. A fast and high-capacity electromagnetic solution for highspeed IC design. [Citation Graph (, )][DBLP]


  2. Impedance extraction for 3-D structures with multiple dielectrics using preconditioned boundary element method. [Citation Graph (, )][DBLP]


  3. Statistical analysis of RF circuits using combined circuit simulator-full wave field solver approach. [Citation Graph (, )][DBLP]


  4. Slot allocation using logical networks for TDM virtual-circuit configuration for network-on-chip. [Citation Graph (, )][DBLP]


  5. Run-time adaptive on-chip communication scheme. [Citation Graph (, )][DBLP]


  6. Using functional independence conditions to optimize the performance of latency-insensitive systems. [Citation Graph (, )][DBLP]


  7. A geometric approach for early power grid verification using current constraints. [Citation Graph (, )][DBLP]


  8. Stochastic extended Krylov subspace method for variational analysis of on-chip power grid networks. [Citation Graph (, )][DBLP]


  9. Parallel domain decomposition for simulation of large-scale power grids. [Citation Graph (, )][DBLP]


  10. Fast exact Toffoli network synthesis of reversible logic. [Citation Graph (, )][DBLP]


  11. A novel synthesis algorithm for reversible circuits. [Citation Graph (, )][DBLP]


  12. Checking equivalence of quantum circuits and states. [Citation Graph (, )][DBLP]


  13. A self-adjusting clock tree architecture to cope with temperature variations. [Citation Graph (, )][DBLP]


  14. Exploiting STI stress for performance. [Citation Graph (, )][DBLP]


  15. Automating post-silicon debugging and repair. [Citation Graph (, )][DBLP]


  16. Practical method for obtaining a feasible integer solution in hierarchical layout optimization. [Citation Graph (, )][DBLP]


  17. Monte-Carlo driven stochastic optimization framework for handling fabrication variability. [Citation Graph (, )][DBLP]


  18. Gate sizing by Lagrangian relaxation revisited. [Citation Graph (, )][DBLP]


  19. An efficient algorithm for statistical circuit optimization using Lagrangian relaxation. [Citation Graph (, )][DBLP]


  20. Unified adaptivity optimization of clock and logic signals. [Citation Graph (, )][DBLP]


  21. Incremental component implementation selection: enabling ECO in compositional system synthesis. [Citation Graph (, )][DBLP]


  22. Exploiting hierarchy and structure to efficiently solve graph coloring as SAT. [Citation Graph (, )][DBLP]


  23. Finding linear building-blocks for RTL synthesis of polynomial datapaths with fixed-size bit-vectors. [Citation Graph (, )][DBLP]


  24. Enhancing design robustness with reliability-aware resynthesis and logic simulation. [Citation Graph (, )][DBLP]


  25. Data locality enhancement for CMPs. [Citation Graph (, )][DBLP]


  26. Mapping model with inter-array memory sharing for multidimensional signal processing. [Citation Graph (, )][DBLP]


  27. Increasing data-bandwidth to instruction-set extensions through register clustering. [Citation Graph (, )][DBLP]


  28. Optimal polynomial-time interprocedural register allocation for high-level synthesis and ASIP design. [Citation Graph (, )][DBLP]


  29. An efficient algorithm for time separation of events in concurrent systems. [Citation Graph (, )][DBLP]


  30. Design, synthesis and evaluation of heterogeneous FPGA with mixed LUTs and macro-gates. [Citation Graph (, )][DBLP]


  31. Device and architecture concurrent optimization for FPGA transient soft error rate. [Citation Graph (, )][DBLP]


  32. Design methodology to trade off power, output quality and error resiliency: application to color interpolation filtering. [Citation Graph (, )][DBLP]


  33. Thermal-aware Steiner routing for 3D stacked ICs. [Citation Graph (, )][DBLP]


  34. Extending systems-on-chip to the third dimension: performance, cost and technological tradeoffs. [Citation Graph (, )][DBLP]


  35. Strategies for improving the parametric yield and profits of 3D ICs. [Citation Graph (, )][DBLP]


  36. Scalable exploration of functional dependency by interpolation and incremental SAT solving. [Citation Graph (, )][DBLP]


  37. Incremental learning approach and SAT model for Boolean matching with don't cares. [Citation Graph (, )][DBLP]


  38. A performance-driven QBF-based iterative logic array representation with applications to verification, debug and test. [Citation Graph (, )][DBLP]


  39. The coming of age of physical synthesis. [Citation Graph (, )][DBLP]


  40. An incremental learning framework for estimating signal controllability in unit-level verification. [Citation Graph (, )][DBLP]


  41. Stimulus generation for constrained random simulation. [Citation Graph (, )][DBLP]


  42. Probabilistic decision diagrams for exact probabilistic analysis. [Citation Graph (, )][DBLP]


  43. Computation of minimal counterexamples by using black box techniques and symbolic methods. [Citation Graph (, )][DBLP]


  44. Approximation algorithm for the temperature-aware scheduling problem. [Citation Graph (, )][DBLP]


  45. Procrastination determination for periodic real-time tasks in leakage-aware dynamic voltage scaling systems. [Citation Graph (, )][DBLP]


  46. The FAST methodology for high-speed SoC/computer simulation. [Citation Graph (, )][DBLP]


  47. A novel SoC design methodology combining adaptive software and reconfigurable hardware. [Citation Graph (, )][DBLP]


  48. Can nano-photonic silicon circuits become an INTRA-chip interconnect technology? [Citation Graph (, )][DBLP]


  49. Hybrid CEGAR: combining variable hiding and predicate abstraction. [Citation Graph (, )][DBLP]


  50. Automated refinement checking of concurrent systems. [Citation Graph (, )][DBLP]


  51. Inductive equivalence checking under retiming and resynthesis. [Citation Graph (, )][DBLP]


  52. A frequency-domain technique for statistical timing analysis of clock meshes. [Citation Graph (, )][DBLP]


  53. Clustering based pruning for statistical criticality computation under process variations. [Citation Graph (, )][DBLP]


  54. Timing budgeting under arbitrary process variations. [Citation Graph (, )][DBLP]


  55. Exploiting symmetry in SAT-based Boolean matching for heterogeneous FPGA technology mapping. [Citation Graph (, )][DBLP]


  56. Combinational and sequential mapping with priority cuts. [Citation Graph (, )][DBLP]


  57. A general model for performance optimization of sequential systems. [Citation Graph (, )][DBLP]


  58. Timing constraint-driven technology mapping for FPGAs considering false paths and multi-clock domains. [Citation Graph (, )][DBLP]


  59. Skew aware polarity assignment in clock tree. [Citation Graph (, )][DBLP]


  60. Efficient multi-layer obstacle-avoiding rectilinear Steiner tree construction. [Citation Graph (, )][DBLP]


  61. A simultaneous bus orientation and bused pin flipping algorithm. [Citation Graph (, )][DBLP]


  62. Optimal bus sequencing for escape routing in dense PCBs. [Citation Graph (, )][DBLP]


  63. Untangling twisted nets for bus routing. [Citation Graph (, )][DBLP]


  64. Low-overhead design technique for calibration of maximum frequency at multiple operating points. [Citation Graph (, )][DBLP]


  65. Variation-aware performance verification using at-speed structural test and statistical timing. [Citation Graph (, )][DBLP]


  66. Estimation of delay test quality and its application to test generation. [Citation Graph (, )][DBLP]


  67. Efficient path delay test generation based on stuck-at test generation using checker circuitry. [Citation Graph (, )][DBLP]


  68. Timing variation-aware high-level synthesis. [Citation Graph (, )][DBLP]


  69. Early planning for clock skew scheduling during register binding. [Citation Graph (, )][DBLP]


  70. Compatibility path based binding algorithm for interconnect reduction in high level synthesis. [Citation Graph (, )][DBLP]


  71. Operation chaining asynchronous pipelined circuits. [Citation Graph (, )][DBLP]


  72. Adaptive post-silicon tuning for analog circuits: concept, analysis and optimization. [Citation Graph (, )][DBLP]


  73. Sensitivity analysis for oscillators. [Citation Graph (, )][DBLP]


  74. Yield-aware analog integrated circuit optimization using geostatistics motivated performance modeling. [Citation Graph (, )][DBLP]


  75. Device-circuit co-optimization for mixed-mode circuit design via geometric programming. [Citation Graph (, )][DBLP]


  76. Modeling, optimization and control of rotary traveling-wave oscillator. [Citation Graph (, )][DBLP]


  77. A methodology for fast and accurate yield factor estimation during global routing. [Citation Graph (, )][DBLP]


  78. Archer: a history-driven global routing algorithm. [Citation Graph (, )][DBLP]


  79. High-performance routing at the nanometer scale. [Citation Graph (, )][DBLP]


  80. BoxRouter 2.0: architecture and implementation of a hybrid and robust global router. [Citation Graph (, )][DBLP]


  81. CacheCompress: a novel approach for test data compression with cache for IP embedded cores. [Citation Graph (, )][DBLP]


  82. A hybrid scheme for compacting test responses with unknown values. [Citation Graph (, )][DBLP]


  83. A selective pattern-compression scheme for power and test-data reduction. [Citation Graph (, )][DBLP]


  84. Methodology for low power test pattern generation using activity threshold control logic. [Citation Graph (, )][DBLP]


  85. ECO timing optimization using spare cells. [Citation Graph (, )][DBLP]


  86. Timing optimization by restructuring long combinatorial paths. [Citation Graph (, )][DBLP]


  87. Engineering change using spare cells with constant insertion. [Citation Graph (, )][DBLP]


  88. Simultaneous input vector selection and dual threshold voltage assignment for static leakage minimization. [Citation Graph (, )][DBLP]


  89. Equalized interconnects for on-chip networks: modeling and optimization framework. [Citation Graph (, )][DBLP]


  90. IntSim: A CAD tool for optimization of multilevel interconnect networks. [Citation Graph (, )][DBLP]


  91. A fast band-matching technique for interconnect inductance modeling. [Citation Graph (, )][DBLP]


  92. Formal verification at higher levels of abstraction. [Citation Graph (, )][DBLP]


  93. Analog placement with common centroid constraints. [Citation Graph (, )][DBLP]


  94. Temperature aware microprocessor floorplanning considering application dependent power load. [Citation Graph (, )][DBLP]


  95. 3D-STAF: scalable temperature and leakage aware floorplanning for three-dimensional integrated circuits. [Citation Graph (, )][DBLP]


  96. Variation-aware task allocation and scheduling for MPSoC. [Citation Graph (, )][DBLP]


  97. A design flow dedicated to multi-mode architectures for DSP applications. [Citation Graph (, )][DBLP]


  98. The design and synthesis of a synchronous and distributed MAC protocol for wireless network-on-chip. [Citation Graph (, )][DBLP]


  99. Selective shielding: a crosstalk-free bus encoding technique. [Citation Graph (, )][DBLP]


  100. Sparse and passive reduction of massively coupled large multiport interconnects. [Citation Graph (, )][DBLP]


  101. Analysis of large clock meshes via harmonic-weighted model order reduction and port sliding. [Citation Graph (, )][DBLP]


  102. Principle Hessian direction based parameter reduction with process variation. [Citation Graph (, )][DBLP]


  103. MOSFET modeling for 45nm and beyond. [Citation Graph (, )][DBLP]


  104. Voltage island-driven floorplanning. [Citation Graph (, )][DBLP]


  105. An ILP algorithm for post-floorplanning voltage-island generation considering power-network planning. [Citation Graph (, )][DBLP]


  106. Module assignment for pin-limited designs under the stacked-Vdd paradigm. [Citation Graph (, )][DBLP]


  107. Yield-driven near-threshold SRAM design. [Citation Graph (, )][DBLP]


  108. Soft-edge flip-flops for improved timing yield: design and optimization. [Citation Graph (, )][DBLP]


  109. Remote activation of ICs for piracy prevention and digital right management. [Citation Graph (, )][DBLP]


  110. A nonlinear cell macromodel for digital applications. [Citation Graph (, )][DBLP]


  111. Including inductance in static timing analysis. [Citation Graph (, )][DBLP]


  112. A robust finite-point based gate model considering process variations. [Citation Graph (, )][DBLP]


  113. Victim alignment in crosstalk aware timing analysis. [Citation Graph (, )][DBLP]


  114. Compact modeling of variational waveforms. [Citation Graph (, )][DBLP]


  115. Multi-layer interconnect performance corners for variation-aware timing analysis. [Citation Graph (, )][DBLP]


  116. An efficient method for statistical circuit simulation. [Citation Graph (, )][DBLP]


  117. A methodology for timing model characterization for statistical static timing analysis. [Citation Graph (, )][DBLP]


  118. Estimation of statistical variation in temporal NBTI degradation and its impact on lifetime circuit performance. [Citation Graph (, )][DBLP]


  119. An efficient method to identify critical gates under circuit aging. [Citation Graph (, )][DBLP]


  120. Efficient computation of current flow in signal wires for reliability analysis. [Citation Graph (, )][DBLP]


  121. The effect of process variation on device temperature in FinFET circuits. [Citation Graph (, )][DBLP]


  122. BioRoute: a network-flow based routing algorithm for digital microfluidic biochips. [Citation Graph (, )][DBLP]


  123. Performance and power evaluation of a 3D CMOS/nanomaterial reconfigurable architecture. [Citation Graph (, )][DBLP]


  124. Fault-tolerant multi-level logic decoder for nanoscale crossbar memory arrays. [Citation Graph (, )][DBLP]


  125. Combining static and dynamic defect-tolerance techniques for nanoscale memory systems. [Citation Graph (, )][DBLP]


  126. An efficient wake-up schedule during power mode transition considering spurious glitches phenomenon. [Citation Graph (, )][DBLP]


  127. Analysis and optimization of power-gated ICs with multiple power gating configurations. [Citation Graph (, )][DBLP]


  128. Sizing and placement of charge recycling transistors in MTCMOS circuits. [Citation Graph (, )][DBLP]


  129. Minimizing leakage power in sequential circuits by using mixed Vt flip-flops. [Citation Graph (, )][DBLP]


  130. Efficient decoupling capacitance budgeting considering operation and process variations. [Citation Graph (, )][DBLP]


  131. Efficient placement of distributed on-chip decoupling capacitors in nanoscale ICs. [Citation Graph (, )][DBLP]


  132. A novel technique for incremental analysis of on-chip power distribution networks. [Citation Graph (, )][DBLP]


  133. Architectural power models for SRAM and CAM structures based on hybrid analytical/empirical techniques. [Citation Graph (, )][DBLP]


  134. Novel wire density driven full-chip routing for CMP variation control. [Citation Graph (, )][DBLP]


  135. Accurate detection for process-hotspots with vias and incomplete specification. [Citation Graph (, )][DBLP]


  136. TIP-OPC: a new topological invariant paradigm for pixel based optical proximity correction. [Citation Graph (, )][DBLP]


  137. A novel intensity based optical proximity correction algorithm with speedup in lithography simulation. [Citation Graph (, )][DBLP]


  138. Stabilizing schemes for piecewise-linear reduced order models via projection and weighting functions. [Citation Graph (, )][DBLP]


  139. Parameterized model order reduction via a two-directional Arnoldi process. [Citation Graph (, )][DBLP]


  140. Efficient VCO phase macromodel generation considering statistical parametric variations. [Citation Graph (, )][DBLP]


  141. Bounding L2 gain system error generated by approximations of the nonlinear vector field. [Citation Graph (, )][DBLP]


  142. Variable domain transformation for linear PAC analysis of mixed-signal systems. [Citation Graph (, )][DBLP]

NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002